SLAZ144I October   2012  – May 2021 MSP430F157

 

  1. 1Functional Advisories
  2. 2Preprogrammed Software Advisories
  3. 3Debug Only Advisories
  4. 4Fixed by Compiler Advisories
  5. 5Nomenclature, Package Symbolization, and Revision Identification
    1. 5.1 Device Nomenclature
    2. 5.2 Package Markings
      1.      RTD64
      2.      PM64
    3. 5.3 Memory-Mapped Hardware Revision (TLV Structure)
  6. 6Advisory Descriptions
    1. 6.1  ADC18
    2. 6.2  ADC25
    3. 6.3  BCL5
    4. 6.4  CPU4
    5. 6.5  DAC4
    6. 6.6  I2C7
    7. 6.7  I2C8
    8. 6.8  I2C9
    9. 6.9  I2C10
    10. 6.10 I2C11
    11. 6.11 I2C12
    12. 6.12 I2C13
    13. 6.13 I2C14
    14. 6.14 I2C15
    15. 6.15 I2C16
    16. 6.16 TA12
    17. 6.17 TA16
    18. 6.18 TA21
    19. 6.19 TAB22
    20. 6.20 TB2
    21. 6.21 TB16
    22. 6.22 TB24
    23. 6.23 US14
    24. 6.24 US15
    25. 6.25 WDG2
    26. 6.26 XOSC4
  7. 7Revision History

6.6 I2C7

I2C Module

Category

Functional

Function

ARDYIFG Interrupt flag generation can fail in I2C slave mode.

Description

When the USART is configured for I2C mode (U0CTL.I2C, SYNC, and I2CEN are set) and the module is configured as an I2C slave (U0CTL.MST=0), the ARDYIFG interrupt flag generation can fail, even when both the I2C stop condition is received and the receive buffer is empty.
This condition occurs when the I2C clock source selected by I2CSSELx is disabled by the Status Register (SR) control signals OSCOFF or SCG1.
In this configuration, the hardware clock activation is enabled by the I2C module. However, if RXRDYIFG is polled to determine data reception, the I2C hardware clock activation may be disabled before the ARDYIFG is generated.

Workaround

(1)Use interrupt service routines using the I2C interrupt vector generator feature (I2CIV) to handle all I2C interrupts.
OR
(2)After detection of I2C Own Address (OAIFG), the selected I2C clock source is enabled by clearing the OSCOFF or SCG1 Status Register (SR) bits. When the ARDYIFG is detected, the OSCOFF or SCG1 in the Status Register (SR) can be set to disable the clock source and return to the desired low power mode operation.
OR
(3)For slave only devices, it is normally not necessary to use ARDYIFG.