SLAZ144I October   2012  – May 2021 MSP430F157

 

  1. 1Functional Advisories
  2. 2Preprogrammed Software Advisories
  3. 3Debug Only Advisories
  4. 4Fixed by Compiler Advisories
  5. 5Nomenclature, Package Symbolization, and Revision Identification
    1. 5.1 Device Nomenclature
    2. 5.2 Package Markings
      1.      RTD64
      2.      PM64
    3. 5.3 Memory-Mapped Hardware Revision (TLV Structure)
  6. 6Advisory Descriptions
    1. 6.1  ADC18
    2. 6.2  ADC25
    3. 6.3  BCL5
    4. 6.4  CPU4
    5. 6.5  DAC4
    6. 6.6  I2C7
    7. 6.7  I2C8
    8. 6.8  I2C9
    9. 6.9  I2C10
    10. 6.10 I2C11
    11. 6.11 I2C12
    12. 6.12 I2C13
    13. 6.13 I2C14
    14. 6.14 I2C15
    15. 6.15 I2C16
    16. 6.16 TA12
    17. 6.17 TA16
    18. 6.18 TA21
    19. 6.19 TAB22
    20. 6.20 TB2
    21. 6.21 TB16
    22. 6.22 TB24
    23. 6.23 US14
    24. 6.24 US15
    25. 6.25 WDG2
    26. 6.26 XOSC4
  7. 7Revision History

6.13 I2C14

I2C Module

Category

Functional

Function

Master SCL phases do not match I2CSCLx settings.

Description

When the USART is configured for I2C mode (U0CTL.I2C, SYNC, and I2CEN are set) and the module is used as an I2C master (U0CTL.MST=1), the generated I2C shift clock (SCL) high and low phases may be one or more I2CIN clock periods longer than defined by I2CSCLH and I2CSCLL. High I2CIN frequencies, large external pull-up resistors, and a large capacitive bus loading on SCL increase the likelihood for this to occur.

Workaround

If possible, use an I2CIN input frequency of 1MHz or less. Additionally, use low-impedance I2C pull-up resistors, preferably in the lower single-digit k-Ohm range, and minimize capacitive load on SCL.