SLAZ144I October   2012  – May 2021 MSP430F157

 

  1. 1Functional Advisories
  2. 2Preprogrammed Software Advisories
  3. 3Debug Only Advisories
  4. 4Fixed by Compiler Advisories
  5. 5Nomenclature, Package Symbolization, and Revision Identification
    1. 5.1 Device Nomenclature
    2. 5.2 Package Markings
      1.      RTD64
      2.      PM64
    3. 5.3 Memory-Mapped Hardware Revision (TLV Structure)
  6. 6Advisory Descriptions
    1. 6.1  ADC18
    2. 6.2  ADC25
    3. 6.3  BCL5
    4. 6.4  CPU4
    5. 6.5  DAC4
    6. 6.6  I2C7
    7. 6.7  I2C8
    8. 6.8  I2C9
    9. 6.9  I2C10
    10. 6.10 I2C11
    11. 6.11 I2C12
    12. 6.12 I2C13
    13. 6.13 I2C14
    14. 6.14 I2C15
    15. 6.15 I2C16
    16. 6.16 TA12
    17. 6.17 TA16
    18. 6.18 TA21
    19. 6.19 TAB22
    20. 6.20 TB2
    21. 6.21 TB16
    22. 6.22 TB24
    23. 6.23 US14
    24. 6.24 US15
    25. 6.25 WDG2
    26. 6.26 XOSC4
  7. 7Revision History

6.2 ADC25

ADC Module

Category

Functional

Function

Write to ADC12CTL0 triggers ADC12 when CONSEQ = 00

Description

If ADC conversions are triggered by the Timer_B module and the ADC12 is in single-channel single-conversion mode (CONSEQ = 00), ADC sampling is enabled by write access to any bit(s) in the ADC12CTL0 register. This is contrary to the expected behavior that only the ADC12 enable conversion bit (ADC12ENC) triggers a new ADC12 sample.

Workaround

When operating the ADC12 in CONSEQ=00 and a Timer_B output is selected as the sample and hold source, temporarily clear the ADC12ENC bit before writing to other bits in the ADC12CTL0 register. The following capture trigger can then be re-enabled by setting ADC12ENC = 1.