SLAZ157J October   2012  – May 2021 MSP430F2101

 

  1. 1Functional Advisories
  2. 2Preprogrammed Software Advisories
  3. 3Debug Only Advisories
  4. 4Fixed by Compiler Advisories
  5. 5Nomenclature, Package Symbolization, and Revision Identification
    1. 5.1 Device Nomenclature
    2. 5.2 Package Markings
      1.      DGV20
      2.      PW20
      3.      DW20
      4.      RGE24
    3. 5.3 Memory-Mapped Hardware Revision (TLV Structure)
  6. 6Advisory Descriptions
    1. 6.1  BCL6
    2. 6.2  BCL8
    3. 6.3  BCL9
    4. 6.4  BCL10
    5. 6.5  BCL11
    6. 6.6  BCL12
    7. 6.7  BCL13
    8. 6.8  BCL14
    9. 6.9  BSL5
    10. 6.10 CPU4
    11. 6.11 CPU5
    12. 6.12 CPU6
    13. 6.13 CPU11
    14. 6.14 CPU12
    15. 6.15 CPU13
    16. 6.16 CPU14
    17. 6.17 CPU19
    18. 6.18 CPU45
    19. 6.19 EEM20
    20. 6.20 FLASH16
    21. 6.21 FLASH17
    22. 6.22 FLASH18
    23. 6.23 FLASH19
    24. 6.24 FLASH20
    25. 6.25 FLASH22
    26. 6.26 FLASH24
    27. 6.27 FLASH27
    28. 6.28 FLASH36
    29. 6.29 JTAG15
    30. 6.30 PORT8
    31. 6.31 PORT10
    32. 6.32 SYS15
    33. 6.33 TA12
    34. 6.34 TA16
    35. 6.35 TA21
    36. 6.36 TAB22
    37. 6.37 XOSC5
    38. 6.38 XOSC8
  7. 7Revision History

FLASH24

FLASH Module

Category

Functional

Function

Write or erase emergency exit can cause failures

Description

When a flash write or erase is abruptly terminated, the following flash accesses by the CPU may be unreliable resulting in erroneous code execution. The abrupt termination can be the result of one the following events:
1) The flash controller clock is configured to be sourced by an external crystal. An oscillator fault occurs thus stopping this clock abruptly.
or
2) The Emergency Exit bit (EMEX in FCTL3) when set forces a write or an erase operation to be terminated before normal completion.
or
3) The Enable Emergency Interrupt Exit bit (EEIEX in FCTL1) when set with GIE=1 can lead to an interrupt causing an emergency exit during a Flash operation.

Workaround

1) Use the internal DCO as the flash controller clock provided from MCLK or SMCLK.
or
2) After setting EMEX = 1, wait for a sufficient amount of time before Flash is accessed again.
or
3) No Workaround. Do not use EEIEX bit.