SLAZ168O October 2012 – May 2021 MSP430F2272 , MSP430F2272-Q1
BCL Module
Functional
SMCLK clock source selection from XT1/VLO to DCO
When the MCLK and the SMCLK do not use the DCO, the DCO is off. The DCO does not start if the clock source for SMCLK is changed from XT1/VLO to DCO. As a result, the SMCLK remains high. Note: This is only true for SMCLK. The DCO starts if the clock source of MCLK is set to DCO.
Set clock source of MCLK to DCO by either:
1)setting the selection bits SELMx of BCSCTL2 register to '00' or '01'.
OR
2)setting the OFIFG bit of IFG1 register. Note: This triggers the oscillator fault logic that automatically starts the DCO. Reset the OFIFG bit to further use the XT1/VLO.
For both options, if the XT1/VLO is still required to source MCLK, revert the clock source of MCLK back to XT1/VLO afterwards.