SLAZ173O October   2012  – May 2021 MSP430F2350

 

  1. 1Functional Advisories
  2. 2Preprogrammed Software Advisories
  3. 3Debug Only Advisories
  4. 4Fixed by Compiler Advisories
  5. 5Nomenclature, Package Symbolization, and Revision Identification
    1. 5.1 Device Nomenclature
    2. 5.2 Package Markings
      1.      RHA40
      2.      YFF49
    3. 5.3 Memory-Mapped Hardware Revision (TLV Structure)
  6. 6Advisory Descriptions
    1. 6.1  BCL12
    2. 6.2  BCL13
    3. 6.3  BCL16
    4. 6.4  CPU14
    5. 6.5  CPU19
    6. 6.6  CPU45
    7. 6.7  EEM20
    8. 6.8  FLASH19
    9. 6.9  FLASH22
    10. 6.10 FLASH24
    11. 6.11 FLASH27
    12. 6.12 FLASH36
    13. 6.13 JTAG14
    14. 6.14 PORT10
    15. 6.15 SYS15
    16. 6.16 TA12
    17. 6.17 TA16
    18. 6.18 TA21
    19. 6.19 TAB22
    20. 6.20 TB2
    21. 6.21 TB16
    22. 6.22 TB24
    23. 6.23 USCI15
    24. 6.24 USCI16
    25. 6.25 USCI17
    26. 6.26 USCI18
    27. 6.27 USCI20
    28. 6.28 USCI21
    29. 6.29 USCI22
    30. 6.30 USCI23
    31. 6.31 USCI24
    32. 6.32 USCI25
    33. 6.33 USCI26
    34. 6.34 USCI27
    35. 6.35 USCI29
    36. 6.36 USCI30
    37. 6.37 USCI34
    38. 6.38 USCI35
    39. 6.39 USCI40
    40. 6.40 XOSC5
    41. 6.41 XOSC8
  7. 7Revision History

6.3 BCL16

BCL Module

Category

Functional

Function

SMCLK clock source selection from XT1/VLO to DCO

Description

When the MCLK and the SMCLK do not use the DCO, the DCO is off. The DCO does not start if the clock source for SMCLK is changed from XT1/VLO to DCO. As a result, the SMCLK remains high. Note: This is only true for SMCLK. The DCO starts if the clock source of MCLK is set to DCO.

Workaround

Set clock source of MCLK to DCO by either:

1)setting the selection bits SELMx of BCSCTL2 register to '00' or '01'.

OR

2)setting the OFIFG bit of IFG1 register. Note: This triggers the oscillator fault logic that automatically starts the DCO. Reset the OFIFG bit to further use the XT1/VLO.


For both options, if the XT1/VLO is still required to source MCLK, revert the clock source of MCLK back to XT1/VLO afterwards.