SLAZ182P October   2012  – May 2021 MSP430F248

 

  1. 1Functional Advisories
  2. 2Preprogrammed Software Advisories
  3. 3Debug Only Advisories
  4. 4Fixed by Compiler Advisories
  5. 5Nomenclature, Package Symbolization, and Revision Identification
    1. 5.1 Device Nomenclature
    2. 5.2 Package Markings
      1.      PM64
      2.      RGC64
    3. 5.3 Memory-Mapped Hardware Revision (TLV Structure)
  6. 6Advisory Descriptions
    1. 6.1  ADC25
    2. 6.2  BCL12
    3. 6.3  BCL13
    4. 6.4  BCL15
    5. 6.5  COMP2
    6. 6.6  CPU19
    7. 6.7  FLASH19
    8. 6.8  FLASH24
    9. 6.9  FLASH25
    10. 6.10 FLASH27
    11. 6.11 FLASH36
    12. 6.12 JTAG23
    13. 6.13 PORT11
    14. 6.14 PORT12
    15. 6.15 TA12
    16. 6.16 TA16
    17. 6.17 TA21
    18. 6.18 TAB22
    19. 6.19 TB2
    20. 6.20 TB16
    21. 6.21 TB24
    22. 6.22 USCI20
    23. 6.23 USCI21
    24. 6.24 USCI22
    25. 6.25 USCI23
    26. 6.26 USCI24
    27. 6.27 USCI25
    28. 6.28 USCI26
    29. 6.29 USCI28
    30. 6.30 USCI30
    31. 6.31 USCI34
    32. 6.32 USCI35
    33. 6.33 USCI40
    34. 6.34 XOSC5
    35. 6.35 XOSC6
    36. 6.36 XOSC8
  7. 7Revision History

6.20 TB16

TB Module

Category

Functional

Function

First increment of TBR erroneous when IDx > 00

Description

The first increment of TBR after any timer clear event (POR/TBCLR) happens immediately following the first positive edge of the selected clock source (INCLK, SMCLK, ACLK, or TBCLK). This is independent of the clock input divider settings (ID0, ID1). All following TBR increments are performed correctly with the selected IDx settings.

Workaround

None