SLAZ212H October   2012  – May 2021 MSP430F447

 

  1. 1Functional Advisories
  2. 2Preprogrammed Software Advisories
  3. 3Debug Only Advisories
  4. 4Fixed by Compiler Advisories
  5. 5Nomenclature, Package Symbolization, and Revision Identification
    1. 5.1 Device Nomenclature
    2. 5.2 Package Markings
      1.      PZ100
    3. 5.3 Memory-Mapped Hardware Revision (TLV Structure)
  6. 6Advisory Descriptions
    1. 6.1  ADC9
    2. 6.2  ADC10
    3. 6.3  ADC13
    4. 6.4  ADC18
    5. 6.5  ADC25
    6. 6.6  CPU4
    7. 6.7  FLL3
    8. 6.8  MPY2
    9. 6.9  PORT3
    10. 6.10 TA12
    11. 6.11 TA16
    12. 6.12 TA21
    13. 6.13 TAB22
    14. 6.14 TB2
    15. 6.15 TB14
    16. 6.16 TB16
    17. 6.17 TB24
    18. 6.18 US13
    19. 6.19 US14
    20. 6.20 US15
    21. 6.21 WDG2
    22. 6.22 XOSC9
  7. 7Revision History

6.7 FLL3

FLL Module

Category

Functional

Function

FLLDx = 11 for /8 may generate an unstable MCLK frequency

Description

When setting the FLL to higher frequencies using FLLDx = 11 (/8) the output frequency of the FLL may have a larger frequency variation (e.g. averaged over 2sec) as well as a lower average output frequency than expected when compared to the other FLLDx bit settings.

Workaround

None