SLAZ224P October   2012  – May 2021 MSP430F46191

 

  1. 1Functional Advisories
  2. 2Preprogrammed Software Advisories
  3. 3Debug Only Advisories
  4. 4Fixed by Compiler Advisories
  5. 5Nomenclature, Package Symbolization, and Revision Identification
    1. 5.1 Device Nomenclature
    2. 5.2 Package Markings
      1.      ZQW113
      2.      PZ100
    3. 5.3 Memory-Mapped Hardware Revision (TLV Structure)
  6. 6Advisory Descriptions
    1. 6.1  CPU8
    2. 6.2  CPU16
    3. 6.3  CPU19
    4. 6.4  DMA3
    5. 6.5  DMA4
    6. 6.6  FLL3
    7. 6.7  FLL6
    8. 6.8  LCDA5
    9. 6.9  LCDA7
    10. 6.10 RTC1
    11. 6.11 TA12
    12. 6.12 TA16
    13. 6.13 TA18
    14. 6.14 TA21
    15. 6.15 TAB22
    16. 6.16 TB2
    17. 6.17 TB16
    18. 6.18 TB18
    19. 6.19 TB24
    20. 6.20 USCI16
    21. 6.21 USCI19
    22. 6.22 USCI20
    23. 6.23 USCI21
    24. 6.24 USCI22
    25. 6.25 USCI23
    26. 6.26 USCI24
    27. 6.27 USCI25
    28. 6.28 USCI26
    29. 6.29 USCI27
    30. 6.30 USCI30
    31. 6.31 USCI34
    32. 6.32 USCI35
    33. 6.33 USCI40
    34. 6.34 WDG2
    35. 6.35 XOSC5
    36. 6.36 XOSC8
    37. 6.37 XOSC9
  7. 7Revision History

6.2 CPU16

CPU Module

Category

Compiler-Fixed

Function

Indexed addressing with instructions calla, mova and bra.

Description

With indexed addressing mode and instructions calla, mova, and bra, it is not possible to reach memory above 64k if the register content is < 64k.

Example: Assume R5 = FFFEh. The instruction calla 0004h(R5) will result in a 20-bit call of address 0002h instead of 10002h.

Workaround

- Use different addressing mode to reach memory above 64k.
- First use adda [index],[Rx] to calculate address in upper memory and then do a calla [Rx]

Refer to the table below for compiler-specific fix implementation information.

IDE/Compiler Version Number Notes
IAR Embedded Workbench IAR EW430 v6.30.1 or later
TI MSP430 Compiler Tools (Code Composer Studio) Fix not available
MSP430 GNU Compiler (MSP430-GCC) Fix not available