SLAZ270AB October 2012 – May 2021 MSP430F5326
ADC Module
Functional
Integral and differential non-linearity exceed specifications
The ADC12_A integral and differential non-linearity may exceed the limits specified in the data sheet under the following conditions:
- If the internal voltage reference generator is used
and
- If the reference voltage is not buffered off-chip
and
- If fADC12CLK > 2.7 MHz
The non-linearity can be up to tens of LSBs. This is due to the internal reference buffer providing insufficient drive for the switched capacitor array of the ADC12_A.
(1) Turn on the output of the internal voltage reference to increase the drive strength of the reference to the ADC_12 core:
- If REFMSTR bit in REFCTL0 is 0 (allowing Shared REF to be controlled by ADC_A reference control bits)
Set ADC12REFON bit in ADC12CTL0 = 1
and
Set ADC12REFOUT bit in ADC12CTL2 = 1
- If REFMSTR bit in REFCTL0 is 1
Set REFON and REFOUT bits in REFCTL0 = 1
OR
(2) Ensure fADC12CLK < 2.7 MHz. Depending on the frequency of the source of fADC12CLK (ACLK, MCLK, SMCLK, or MODOSC), select the divider bits accordingly.
- If fADC12CLK = MODOSC
(ADC12OSC) ADC12CTL1 |= ADC12DIV_1; // Divide clock by 2
- If fADC12CLK = ACLK/SMCLK/MCLK > 2.7 MHz.
Use ADC12DIVx and/or ADC12PDIVx bits to reduce the selected clock frequency to between 0.45 MHz and 2.7 MHz.