SLAZ271AB October   2012  – May 2021 MSP430F5327

 

  1. 1Functional Advisories
  2. 2Preprogrammed Software Advisories
  3. 3Debug Only Advisories
  4. 4Fixed by Compiler Advisories
  5. 5Nomenclature, Package Symbolization, and Revision Identification
    1. 5.1 Device Nomenclature
    2. 5.2 Package Markings
      1.      PN80
    3. 5.3 Memory-Mapped Hardware Revision (TLV Structure)
  6. 6Advisory Descriptions
    1. 6.1  ADC25
    2. 6.2  ADC27
    3. 6.3  ADC29
    4. 6.4  ADC42
    5. 6.5  ADC69
    6. 6.6  BSL6
    7. 6.7  BSL7
    8. 6.8  COMP10
    9. 6.9  CPU21
    10. 6.10 CPU22
    11. 6.11 CPU23
    12. 6.12 CPU26
    13. 6.13 CPU27
    14. 6.14 CPU28
    15. 6.15 CPU29
    16. 6.16 CPU30
    17. 6.17 CPU31
    18. 6.18 CPU32
    19. 6.19 CPU33
    20. 6.20 CPU34
    21. 6.21 CPU35
    22. 6.22 CPU37
    23. 6.23 CPU39
    24. 6.24 CPU40
    25. 6.25 CPU47
    26. 6.26 DMA4
    27. 6.27 DMA7
    28. 6.28 DMA8
    29. 6.29 DMA10
    30. 6.30 EEM9
    31. 6.31 EEM11
    32. 6.32 EEM13
    33. 6.33 EEM14
    34. 6.34 EEM15
    35. 6.35 EEM16
    36. 6.36 EEM17
    37. 6.37 EEM19
    38. 6.38 EEM21
    39. 6.39 EEM23
    40. 6.40 FLASH33
    41. 6.41 FLASH34
    42. 6.42 FLASH35
    43. 6.43 FLASH37
    44. 6.44 JTAG20
    45. 6.45 JTAG26
    46. 6.46 JTAG27
    47. 6.47 LDO1
    48. 6.48 MPY1
    49. 6.49 PMAP1
    50. 6.50 PMM9
    51. 6.51 PMM10
    52. 6.52 PMM11
    53. 6.53 PMM12
    54. 6.54 PMM14
    55. 6.55 PMM15
    56. 6.56 PMM17
    57. 6.57 PMM18
    58. 6.58 PMM20
    59. 6.59 PORT15
    60. 6.60 PORT16
    61. 6.61 PORT19
    62. 6.62 PORT24
    63. 6.63 RTC3
    64. 6.64 RTC6
    65. 6.65 SYS10
    66. 6.66 SYS12
    67. 6.67 SYS14
    68. 6.68 SYS16
    69. 6.69 TAB23
    70. 6.70 USCI26
    71. 6.71 USCI30
    72. 6.72 USCI31
    73. 6.73 USCI34
    74. 6.74 USCI35
    75. 6.75 USCI39
    76. 6.76 USCI40
    77. 6.77 WDG4
  7. 7Revision History

6.45 JTAG26

JTAG Module

Category

Debug

Function

LPMx.5 Debug Support Limitations

Description

The JTAG connection to the device might fail at device-dependent low or high supply voltage levels if the LPMx.5 debug support feature is enabled. To avoid a potentially unreliable debug session or general issues with JTAG device connectivity and the resulting bad customer experience Texas Instruments has chosen to remove the LPMx.5 debug support feature from common MSP430 IDEs including TIs Code Composer Studio 6.1.0 with msp430.emu updated to version 6.1.0.7 and IARs Embedded Workbench 6.30.2,  which are based on the MSP430 debug stack MSP430.DLL 3.5.0.1  http://www.ti.com/tool/MSPDS

TI plans to re-introduce this feature in limited capacity in a future release of the debug stack by providing an IDE override option for customers to selectively re-activate LPMx.5 debug support if needed. Note that the limitations and supply voltage dependencies outlined in this erratum will continue to apply.

For additional information on how the LPMx.5 debug support is handled within the MSP430 IDEs including possible workarounds on how to debug applications using LPMx.5 without toolchain support refer to Code Composer Studio User's Guide for MSP430 chapter F.4 and IAR Embedded Workbench User's Guide for MSP430 chapter 2.2.5.

Workaround

1.        If LPMx.5 debug support is deemed functional and required in a given scenario:

a)      Do not update the IDE to continue using a previous version of the debug stack such as MSP430.DLL v3.4.3.4.

OR

b)      Roll back the debug stack by either performing a clean re-installation of a previous version of the IDE or by manually replacing the debug stack with a prior version such as MSP430.DLL v3.4.3.4 that can be obtained from http://www.ti.com/tool/MSPDS.  

2.       In case JTAG connectivity fails during the LPMx.5 debug mode, the device supply voltage level needs to be raised or lowered until the connection is working.

Do not enable the LPMx.5 debug support feature during production programming.