SLAZ279AA October 2012 – May 2021 MSP430F5418
UCS Module
Functional
LPM modes not entered properly when MCLK < ACLK
When MCLK is sourced by XT1, XT2 or REFO clock sources and MCLK is slower than ACLK the low power modes are not entered properly.
This applies when the MCLK clock divider is greater than the ACLK clock divider setting.
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