SLAZ280AC October   2012  – May 2021 MSP430F5418A

 

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6.57 SYS10

SYS Module

Category

Functional

Function

BSL entry sequence is subject to specific timing requirements

Description

The BSL entry sequence requires that the low phase of the TEST/SBWTCK pin does not exceed 15us. This timing requirement is faster than most PC serial ports can provide, as shown in the following picture. If this requirement is not met, the entry sequence fails and the SYSBSLIND is not set.


GUID-20201119-CA0I-SPHQ-VLKS-5FJWWRG71J0G-low.png

Workaround

An external hardware solution is recommended to provide the appropriate BSL entry sequence. See http://processors.wiki.ti.com/index.php/BSL_(MSP430) for recommendations on available BSL hardware.