SLAZ283AA October   2012  – May 2021 MSP430F5435

 

  1.   1
  2.   2
  3.   3
  4.   4
  5.   5
    1.     6
    2.     7
      1.      8
    3.     9
  6.   10
    1.     11
    2.     12
    3.     13
    4.     14
    5.     15
    6.     16
    7.     17
    8.     18
    9.     19
    10.     20
    11.     21
    12.     22
    13.     23
    14.     24
    15.     25
    16.     26
    17.     27
    18.     28
    19.     29
    20.     30
    21.     31
    22.     32
    23.     33
    24.     34
    25.     35
    26.     36
    27.     37
    28.     38
    29.     39
    30.     40
    31.     41
    32.     42
    33.     43
    34.     44
    35.     45
    36.     46
    37.     47
    38.     48
    39.     49
    40.     50
    41.     51
    42.     52
    43.     53
    44.     54
    45.     55
    46.     56
    47.     57
    48.     58
    49.     59
    50.     60
    51.     61
    52.     62
    53.     63
    54.     64
    55.     65
    56.     66
    57.     67
    58.     68
    59.     69
    60.     70
    61.     71
    62.     72
    63.     73
    64.     74
    65.     75
    66.     76
    67.     77
    68.     78
    69.     79
    70.     80
    71.     81
    72.     82
    73.     83
    74.     84
    75.     85
    76.     86
    77.     87
    78.     88
    79.     89
    80.     90
    81.     91
    82.     92
    83.     93
    84.     94
    85.     95
    86.     96
    87.     97
    88.     98
    89.     99
    90.     100
    91.     101
    92.     102
    93.     103
    94.     104
    95.     105
    96.     106
    97.     107
    98.     108
    99.     109
    100.     110
    101.     111
    102.     112
    103.     113
    104.     114
    105.     115
    106.     116
    107.     117
    108.     118
    109.     119
    110.     120
    111.     121
    112.     122
    113.     123
    114.     124
    115.     125
    116.     126
    117.     127
    118.     128
  7.   129

6.20 CPU29

CPU Module

Category

Compiler-Fixed

Function

Using a certain instruction sequence to enter low power mode(s) affects the instruction width of the first instruction in an NMI ISR

Description

If there is a pending NMI request when the CPU enters a low power mode (LPMx) using an instruction of Indexed source addressing mode, and that instruction is followed by a 20-bit wide instruction of Register source and destination addressing modes, the first instruction of the ISR is executed as a 20-bit wide instruction.

Example:
main:
         ...
         MOV.W  [indexed],SR          ; Enter LPMx
         MOVX.A [register],[register] ; 20-bit wide instruction
         ...

ISR_start:
         MOV.B  [indexed],[register]  ; ERROR - Executed as a 20-bit instruction!



Note: [] indicates addressing mode

Workaround

1. Insert a NOP or a __no_operation() intrinsic function following the instruction that enters the LPMx using indexed addressing mode

OR

2. Use a NOP or a __no_operation() intrinsic function as first instruction in the ISR

OR

3. Do not use the indexed mode to enter LPMx


Refer to the table below for compiler-specific fix implementation information.

IDE/Compiler Version Number Notes
IAR Embedded Workbench IAR EW430 v6.20 until v6.40 User is required to add the compiler or assembler flag option below. --hw_workaround=nop_after_lpm
IAR Embedded Workbench IAR EW430 v6.40 or later Workaround is automatically enabled
TI MSP430 Compiler Tools (Code Composer Studio) v4.1.3 or later
MSP430 GNU Compiler (MSP430-GCC) MSP430-GCC 4.9 build 167