SLAZ296AC October   2012  – August 2021 MSP430F5505

 

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6.1 ADC30

ADC Module

Category

Functional

Function

ADC hangs when a slow ADC clock source is used

Description

When using ADC10SC bit to software trigger ADC conversions, the ADC10 state machine may hang (that is, no further interrupts are generated) if the ADC clock source (ADC10CLK) is significantly slower than the system clock (MCLK). This issue can be observed when ADC10CLK < MCLK/8. If the ADC conversions are re-triggered by setting the ADC10SC bit before eight MCLK cycles have elapsed since the ADCIFG interrupt bit is set or the ADC10BUSY bit is reset, then this behavior can be seen.

Workaround

- Use MODOSC or any clock that is > MCLK/8 as ADC10CLK
or
- When using a clock source < = MCLK/8 as ADC10CLK, ensure the application code provides a delay of at least one ADC10CLK cycle before setting the ADC10SC bit again.