Advisories that affect the device's operation, function, or parametrics.
✓ The check mark indicates that the issue is present in the specified revision.
Advisories that are resolved by compiler workaround. Refer to each advisory for the IDE and compiler versions with a workaround.
✓ The check mark indicates that the issue is present in the specified revision.
Refer to the following MSP430 compiler documentation for more details about the CPU bugs workarounds.
TI MSP430 Compiler Tools (Code Composer Studio IDE)
MSP430 GNU Compiler (MSP430-GCC)
IAR Embedded Workbench
The revision of the device can be identified by the revision letter on the Package Markings or by the HW_ID located inside the TLV structure of the device.
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all MSP MCU devices. Each MSP MCU commercial family member has one of two prefixes: MSP or XMS. These prefixes represent evolutionary stages of product development from engineering prototypes (XMS) through fully qualified production devices (MSP).
XMS – Experimental device that is not necessarily representative of the final device's electrical specifications
MSP – Fully qualified production device
Support tool naming prefixes:
X: Development-support product that has not yet completed Texas Instruments internal qualification testing.
null: Fully-qualified development-support product.
XMS devices and X development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
MSP devices have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (XMS) have a greater failure rate than the standard production devices. TI recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the temperature range, package type, and distribution format.
LQFP (PZ) 100 Pin
LQFP (PN), 80 Pin
Die Revision | TLV Hardware Revision |
---|---|
Rev A | 10h |
Further guidance on how to locate the TLV structure and read out the HW_ID can be found in the device User's Guide.
ADC Module
Functional
Erroneous ADC10 results in extended sample mode
If the extended sample mode is selected (ADC10SHP = 0) and the ADC10CLK is asynchronous to the SHI signal, the ADC10 may generate erroneous results.
1) Use the pulse sample mode (ADC10SHP=1)
OR
2) Use a synchronous clock for ADC10 and the SHI signal.
ADC Module
Functional
ADC stops converting when successive ADC is triggered before the previous conversion ends
Subsequent ADC conversions are halted if a new ADC conversion is triggered while ADC is busy. ADC conversions are triggered manually or by a timer. The affected ADC modes are:
- sequence-of-channels
- repeat-single-channel
- repeat-sequence-of-channels (ADC12CTL1.ADC12CONSEQx)
In addition, the timer overflow flag cannot be used to detect an overflow (ADC12IFGR2.ADC12TOVIFG).
1. For manual trigger mode (ADC12CTL0.ADC12SC), ensure each ADC conversion is completed by first checking ADC12CTL1.ADC12BUSY bit before starting a new conversion.
2. For timer trigger mode (ADC12CTL1.ADC12SHP), ensure the timer period is greater than the ADC sample and conversion time.
To recover the conversion halt:
1. Disable ADC module (ADC12CTL0.ADC12ENC = 0 and ADC12CTL0.ADC12ON = 0)
2. Re-enable ADC module (ADC12CTL0.ADC12ON = 1 and ADC12CTL0.ADC12ENC = 1)
3. Re-enable conversion
ADC Module
Functional
ADC stops operating if ADC clock source is changed from SMCLK to another source while SMCLKOFF = 1.
When SMCLK is used as the clock source for the ADC (ADC12CTL1.ADC12SSELx = 11) and CSCTL4.SMCLKOFF = 1, the ADC will stop operating if the ADC clock source is changed by user software (e.g. in the ISR) from SMCLK to a different clock source. This issue appears only for the ADC12CTL1.ADC12DIVx settings /3/5/7. The hang state can be recovered by PUC/POR/BOR/Power cycle.
1. Set CSCTL4.SMCLKOFF = 0 before switch ADC clock source.
OR
2. Only use ADC12CTL1.ADC12DIVx as /1, /2, /4, /6, /8
AUXPMM Module
Functional
AUXVCC1/AUXVCC2 can not be switched back to DVCC
When the system is running with the AUXVCC1 supply after DVCC/AVCC is lost, if the AUXVCC1 voltage goes lower than SVSH setting for POR and above BORH level, the system can not switch back to DVCC after DVCC ramps back up again.
Similarly, when the system is running with the AUXVCC2 supply after DVCC/AVCC is lost, if the AUXVCC2 voltage goes lower than SVSH setting for POR and above BORH level, the system can not switch back to DVCC after DVCC ramps back up again.
When the system is running with the AUXVCC1 supply, use SVMH to monitor AUXVCC1 voltage. When AUXVCC1 is lower than the SVMH setting, the program drives the chip into LPMx.5. After DVCC ramps up back again, trigger one of the wake up pins. The power supply could be switched back to DVCC again.
When the system is running with the AUXVCC2 supply, use SVMH to monitor AUXVCC2 voltage. When AUXVCC2 is lower than the SVMH setting, the program drives the chip into LPMx.5. After DVCC ramps up back again, trigger one of the wake up pins. The power supply could be switched back to DVCC again.
AUXPMM Module
Functional
Latch-up in AUXPMM
Latch-up current can appear at the AUXPMM module supply pins in the following two scenarios:
Scenario 1: When the AUXPMM is configured for hardware- or software-controlled switching and the module switches from DVCC to AUXVCC2, latch-up current can appear at AUXVCC2 at the switching point defined by SVSMHCTL.SVSMHRRL (or AUXCTL2.AUX0LVLx). The probability for this event to occur depends on:
a) Operating temperature (higher temperatures increase probability)
b) External AUXVCC2 voltage level (higher voltages increase probability)
c) SVSMHRRL level (lower levels increase probability) defining the switching level in hardware-controlled mode
d) AUX0LVLx level (lower levels increase probability) defining the switching level in software-controlled mode (applicable to DVCC only)
Scenario 2: When a battery is connected to DVCC, AUXVCC1 or AUXVCC2 as the first voltage supply, due to the low internal resistance of the battery a very fast rise time is seen by the AUXPMM and latch-up current can appear at the connected supply if:
a) Rise times are in the range of 140 kV/s (faster rise times increase probability)
b) Device operates at temperatures of 75 deg C and above (higher temperatures increase probability)
The latch-up current disappears after complete power cycles of all supply sources.
For scenario 1:
- Increase SVSMRRL to a level above maximum external voltage expected on AUXVCC2. SVSMRRL = 6 or 7 (requires VCORE level of 3) is applicable for AUXVCC2 of up to maximum voltage, 3.58V, while a lower SVSMRRL setting can be selected if a lower voltage (e.g. 3.3V) is expected on AUXVCC2.
Or
- Connect all 3 supplies via 3 external diodes to DVCC and realize the switching externally without using the internal AUXPMM switches. See application report "Implementation of a Three-Phase Electronic Watt-Hour Meter Using the MSP430F471xx" for details.
Or
- Use AUXVCC1 instead of AUXVCC2 for backup supply
For scenario 2:
Limit the supply voltage ramp up time through a series resistor (e.g. 10 Ohm) in the critical supply path. Side effects such as voltage dips due to high current consumption of the device need to be considered.
BSL Module
Software in ROM
BSL does not start after waking up from LPMx.5
When waking up from LPMx.5 mode, the BSL does not start as it does not clear the Lock I/O bit (LOCKLPM5 bit in PM5CTL0 register) on start-up.
1. Upgrade the device BSL to the latest version (see Creating a Custom Flash-Based Bootstrap Loader (BSL) Application Note - SLAA450 for more details)
OR
2. Do not use LOCKLPM5 bit (LPMx.5) if the BSL is used but cannot be upgraded.
BSL Module
Software in ROM
BSL request to unlock the JTAG
The feature in the BSL to keep the JTAG unlocked by setting the bit BSL_REQ_JTAG_OPEN in the return value has been disabled in this device.
None
CPU Module
Compiler-Fixed
Using POPM instruction on Status register may result in device hang up
When an active interrupt service request is pending and the POPM instruction is used to set the Status Register (SR) and initiate entry into a low power mode , the device may hang up.
None. It is recommended not to use POPM instruction on the Status Register.
Refer to the table below for compiler-specific fix implementation information.
IDE/Compiler | Version Number | Notes |
---|---|---|
IAR Embedded Workbench | Not affected | |
TI MSP430 Compiler Tools (Code Composer Studio) | v4.0.x or later | User is required to add the compiler or assembler flag option below. --silicon_errata=CPU21 |
MSP430 GNU Compiler (MSP430-GCC) | MSP430-GCC 4.9 build 167 or later |
CPU Module
Compiler-Fixed
Indirect addressing mode with the Program Counter as the source register may produce unexpected results
When using the indirect addressing mode in an instruction with the Program Counter (PC) as the source operand, the instruction that follows immediately does not get executed.
For example in the code below, the ADD instruction does not get executed.
mov @PC, R7
add #1h, R4
Refer to the table below for compiler-specific fix implementation information.
IDE/Compiler | Version Number | Notes |
---|---|---|
IAR Embedded Workbench | Not affected | |
TI MSP430 Compiler Tools (Code Composer Studio) | v4.0.x or later | User is required to add the compiler or assembler flag option below. --silicon_errata=CPU22 |
MSP430 GNU Compiler (MSP430-GCC) | MSP430-GCC 4.9 build 167 or later |
CPU Module
Functional
PC corruption when single-stepping through flash erase
When single-stepping over code that initiates an INFOD Flash memory erase, the program counter is corrupted.
None.
NOTE: This erratum applies to debug mode only.
CPU Module
Compiler-Fixed
PC is corrupted when executing jump/conditional jump instruction that is followed by instruction with PC as destination register or a data section
If the value at the memory location immediately following a jump/conditional jump instruction is 0X40h or 0X50h (where X = don't care), which could either be an instruction opcode (for instructions like RRCM, RRAM, RLAM, RRUM) with PC as destination register or a data section (const data in flash memory or data variable in
RAM), then the PC value is auto-incremented by 2 after the jump instruction is executed; therefore, branching to a wrong address location in code and leading to wrong program execution.
For example, a conditional jump instruction followed by data section (0140h).
@0x8012 Loop DEC.W R6
@0x8014 DEC.W R7
@0x8016 JNZ Loop
@0x8018 Value1 DW 0140h
In assembly, insert a NOP between the jump/conditional jump instruction and program code with instruction that contains PC as destination register or the data section.
Refer to the table below for compiler-specific fix implementation information.
IDE/Compiler | Version Number | Notes |
---|---|---|
IAR Embedded Workbench | IAR EW430 v5.51 or later | For the command line version add the following information Compiler: --hw_workaround=CPU40 Assembler:-v1 |
TI MSP430 Compiler Tools (Code Composer Studio) | v4.0.x or later | User is required to add the compiler or assembler flag option below. --silicon_errata=CPU40 |
MSP430 GNU Compiler (MSP430-GCC) | Not affected |
CPU Module
Functional
POPM peforms unexpected memory access and can cause VMAIFG to be set
When the POPM assembly instruction is executed, the last Stack Pointer increment is followed by an unintended read access to the memory. If this read access is performed on vacant memory, the VMAIFG will be set and can trigger the corresponding interrupt (SFRIE1.VMAIE) if it is enabled. This issue occurs if the POPM assembly instruction is performed up to the top of the STACK.
If the user is utilizing C, they will not be impacted by this issue. All TI/IAR/GCC pre-built libraries are not impacted by this bug. To ensure that POPM is never executed up to the memory border of the STACK when using assembly it is recommended to either
1. Initialize the SP to
a. TOP of STACK - 4 bytes if POPM.A is used
b. TOP of STACK - 2 bytes if POPM.W is used
OR
2. Use the POPM instruction for all but the last restore operation. For the the last restore operation use the POP assembly instruction instead.
For instance, instead of using:
POPM.W #5,R13
Use:
POPM.W #4,R12
POP.W R13
Refer to the table below for compiler-specific fix implementation information.
IDE/Compiler | Version Number | Notes |
---|---|---|
IAR Embedded Workbench | Not affected | C code is not impacted by this bug. User using POPM instruction in assembler is required to implement the above workaround manually. |
TI MSP430 Compiler Tools (Code Composer Studio) | Not affected | C code is not impacted by this bug. User using POPM instruction in assembler is required to implement the above workaround manually. |
MSP430 GNU Compiler (MSP430-GCC) | Not affected | C code is not impacted by this bug. User using POPM instruction in assembler is required to implement the above workaround manually. |