SLAZ366Q October   2012  – May 2021 MSP430FG4616

 

  1. 1Functional Advisories
  2. 2Preprogrammed Software Advisories
  3. 3Debug Only Advisories
  4. 4Fixed by Compiler Advisories
  5. 5Nomenclature, Package Symbolization, and Revision Identification
    1. 5.1 Device Nomenclature
    2. 5.2 Package Markings
      1.      ZQW113
      2.      PZ100
      3.      ZCA113
    3. 5.3 Memory-Mapped Hardware Revision (TLV Structure)
  6. 6Advisory Descriptions
    1. 6.1  ADC18
    2. 6.2  ADC25
    3. 6.3  CPU8
    4. 6.4  CPU16
    5. 6.5  CPU19
    6. 6.6  DMA3
    7. 6.7  DMA4
    8. 6.8  FLL3
    9. 6.9  FLL6
    10. 6.10 LCDA5
    11. 6.11 LCDA7
    12. 6.12 RTC1
    13. 6.13 TA12
    14. 6.14 TA16
    15. 6.15 TA18
    16. 6.16 TA21
    17. 6.17 TAB22
    18. 6.18 TB2
    19. 6.19 TB16
    20. 6.20 TB18
    21. 6.21 TB24
    22. 6.22 USCI16
    23. 6.23 USCI19
    24. 6.24 USCI20
    25. 6.25 USCI21
    26. 6.26 USCI22
    27. 6.27 USCI23
    28. 6.28 USCI24
    29. 6.29 USCI25
    30. 6.30 USCI26
    31. 6.31 USCI27
    32. 6.32 USCI30
    33. 6.33 USCI34
    34. 6.34 USCI35
    35. 6.35 USCI40
    36. 6.36 WDG2
    37. 6.37 XOSC5
    38. 6.38 XOSC8
    39. 6.39 XOSC9
  7. 7Revision History

6.7 DMA4

DMA Module

Category

Functional

Function

Corrupted write access to 20-bit DMA registers

Description

When a 20-bit wide write to a DMA address register (DMAxSA or DMAxDA) is interrupted by a DMA transfer, the register contents may be unpredictable.

Workaround

1. Design the application to guarantee that no DMA access interrupts 20-bit wide accesses to the DMA address registers.

OR

2. When accessing the DMA address registers, enable the Read Modify Write disable bit (DMARMWDIS = 1) or temporarily disable all active DMA channels (DMAEN = 0).

OR

3. Use word access for accessing the DMA address registers. Note that this limits the values that can be written to the address registers to 16-bit values (lower 64K of Flash).