SLAZ374AH October   2012  – August 2021 MSP430FR5721

 

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6.19 DMA14

DMA Module

Category

Functional

Function

DMA misses trigger from asynchronous source and all subsequent transfers/triggers

Description

If DMA module is used in edge-triggered mode
AND
the trigger source (e.g. TimerA, TimerB, USCI or ADC10) is running with an asynchronous clock (e.g. MODOSC, VLO or external crystal clock) versus DMA clock (MCLK),
AND
the DMA trigger occurs while the CPU is in active mode, then the DMA module might miss an edge trigger and then all subsequent edge triggers.

This leads to a missing DMA transfer cycle. The DMA size address register (DMAxSZ) will note decrement, and the trigger source (corresponding module flag) is not cleared. Due to this, the expected DMA interrupt is not executed and the DMA hangs.

Workaround

To prevent the issue entirely, run DMA and module from the same clock source(e.g. MCLK, SMCLK with same source as MCLK, etc) to prevent asynchronous events.

To detect the issue:
Use overflow flags found in many modules (e.g. ADC10OVIFG) to detect DMA lockup
OR
Use the WDT at the system-level to detect a hang-up.

After detection, recover operation by clearing the DMA trigger source interrupt flag, clearing the data to be transferred, and re-initializing both the DMA and the module for the trigger source. If the trigger source is unknown, trigger a software BOR reset by setting the PMMSWBOR bit in the PMMCTL0 register.