SLAZ409K October   2012  – May 2021 MSP430G2153

 

  1. 1Functional Advisories
  2. 2Preprogrammed Software Advisories
  3. 3Debug Only Advisories
  4. 4Fixed by Compiler Advisories
  5. 5Nomenclature, Package Symbolization, and Revision Identification
    1. 5.1 Device Nomenclature
    2. 5.2 Package Markings
      1.      RHB32
      2.      N20
      3.      PW20
      4.      PW28
    3. 5.3 Memory-Mapped Hardware Revision (TLV Structure)
  6. 6Advisory Descriptions
    1. 6.1  BCL12
    2. 6.2  CPU4
    3. 6.3  EEM20
    4. 6.4  SYS15
    5. 6.5  TA12
    6. 6.6  TA16
    7. 6.7  TA21
    8. 6.8  TAB22
    9. 6.9  USCI20
    10. 6.10 USCI22
    11. 6.11 USCI23
    12. 6.12 USCI24
    13. 6.13 USCI25
    14. 6.14 USCI26
    15. 6.15 USCI29
    16. 6.16 USCI30
    17. 6.17 USCI34
    18. 6.18 USCI35
    19. 6.19 USCI40
    20. 6.20 XOSC5
  7. 7Revision History

6.9 USCI20

USCI Module

Category

Functional

Function

I2C Mode Multi-master transmitter issue

Description

When configured for I2C master-transmitter mode, and used in a multi-master environment, the USCI module can cause unpredictable bus behavior if all of the following four conditions are true:

1 - Two masters are generating SCL
And
2 - The slave is stretching the SCL low phase of an ACK period while outputting NACK on SDA
And
3 - The slave drives ACK on SDA after the USCI has already released SCL, and then the SCL bus line gets released
And
4 - The transmit buffer has not been loaded before the other master continues communication by driving SCL low

The USCI will remain in the SCL high phase until the transmit buffer is written. After the transmit buffer has been written, the USCI will interfere with the current bus activity and may cause unpredictable bus behavior.

Workaround

1 - Ensure that slave doesn't stretch the SCL low phase of an ACK period
Or
2 - Ensure that the transmit buffer is loaded in time
Or
3 - Do not use the multi-master transmitter mode