SLAZ431K October   2012  – May 2021 MSP430G2403

 

  1. 1Functional Advisories
  2. 2Preprogrammed Software Advisories
  3. 3Debug Only Advisories
  4. 4Fixed by Compiler Advisories
  5. 5Nomenclature, Package Symbolization, and Revision Identification
    1. 5.1 Device Nomenclature
    2. 5.2 Package Markings
      1.      RHB32
      2.      N20
      3.      PW20
      4.      PW28
    3. 5.3 Memory-Mapped Hardware Revision (TLV Structure)
  6. 6Advisory Descriptions
    1. 6.1  BCL12
    2. 6.2  CPU4
    3. 6.3  EEM20
    4. 6.4  SYS15
    5. 6.5  TA12
    6. 6.6  TA16
    7. 6.7  TA21
    8. 6.8  TAB22
    9. 6.9  USCI20
    10. 6.10 USCI22
    11. 6.11 USCI23
    12. 6.12 USCI24
    13. 6.13 USCI25
    14. 6.14 USCI26
    15. 6.15 USCI29
    16. 6.16 USCI30
    17. 6.17 USCI34
    18. 6.18 USCI35
    19. 6.19 USCI40
    20. 6.20 XOSC5
  7. 7Revision History

6.18 USCI35

USCI Module

Category

Functional

Function

Violation of setup and hold times for (repeated) start in I2C master mode

Description

In I2C master mode, the setup and hold times for a (repeated) START, tSU,STA and tHD,STA respectively, can be violated if SCL clock frequency is greater than 50kHz in standard mode (100kbps). As a result, a slave can receive incorrect data or the I2C bus can be stalled due to clock stretching by the slave.

Workaround

If using repeated start, ensure SCL clock frequencies is < 50kHz in I2C standard mode (100 kbps).