SLAZ448G October 2012 – May 2021 MSP430F423A
ESP Module
Functional
Suspending the ESP430CE1
Suspending the ESP430 may create an invalid interrupt which can lead to a reset-like behavior of the module.
Set the bit 0x08 together with the ESPSUSP bit:
bis.w #08h+ESPSUSP, &ESPCTL
This bit also must be cleared when the suspend mode is exited.
bic.w #08h+ESPSUSP, &ESPCTL
NOTE:
- After suspending the ESP430CE1 it can take up to 9 MCLK clock cycles before the CPU can access the SD16 registers.
- An interrupt service routine for the SD16 is required.
// Shut down ESP (set Embedded Signal Processing into
// "Suspend" mode)
// ensure that it is not in measurement or calibration mode,
ESPCTL |= 0x08 + ESPSUSP;
// Set ESP into Suspend Mode
// incl. Bug Fix for Suspend Mode
// wait 9 clocks until proper access to the SD16 is possible
__delay_cycles(9);
MBCTL &= ~(IN0IFG + IN0IE);
// Clear any Pending MB interrupt and disable
// ESP interrupt
SD16CTL &= ~SD16REFON; // Switch Reference off