SLAZ464Z May   2014  – August 2021 MSP430FR5948

 

  1.   1
  2.   2
  3.   3
  4.   4
  5.   5
    1.     6
    2.     7
      1.      8
      2.      9
    3.     10
  6.   11
    1.     12
    2.     13
    3.     14
    4.     15
    5.     16
    6.     17
    7.     18
    8.     19
    9.     20
    10.     21
    11.     22
    12.     23
    13.     24
    14.     25
    15.     26
    16.     27
    17.     28
    18.     29
    19.     30
    20.     31
    21.     32
    22.     33
    23.     34
    24.     35
    25.     36
    26.     37
    27.     38
    28.     39
    29.     40
    30.     41
    31.     42
    32.     43
    33.     44
    34.     45
    35.     46
    36.     47
    37.     48
    38.     49
    39.     50
    40.     51
    41.     52
    42.     53
    43.     54
    44.     55
    45.     56
    46.     57
    47.     58
  7.   59

6.31 GC4

GC Module

Category

Functional

Function

Unexpected PUC is triggered

Description

During execution from FRAM a non-existent uncorrectable bit error can be detected and trigger a PUC if the uncorrectable bit error detection flag is set (GCCTL0.UBDRSTEN = 1). This behavior appears only if:

(1) MCLK is sourced from DCO frequency of 16 MHz

OR

(2) MCLK is sourced by external high frequency clock above 12 MHz at pin HFXIN

OR

(3) MCLK is sourced by High-Frequency crystals (HFXT) above 12 MHz.  

This PUC will not be recognized by the SYSRSTIV register (SYSRSTIV = 0x00).
A PUC RESET will be executed with not defined reset source.
Also the corresponding bit error detection flag is not set  (GCCTL1.UBDIFG = 0).

Workaround

1. Check the reset source for SYSRSTIV = 0 and ignore the reset.

OR

2. Set GCCTL0.UBDRSTEN = 0 to prevent unexpected PUC. NMI event will not be triggered, even if GCCTL0.UBDIE = 1 -> consider GC1 Errata for more details.

OR

3. Set the MCLK to maximum 12MHz to leverage the uncorrectable bit error PUC feature.