SLAZ473AG October 2012 – August 2021 MSP430FR5969 , MSP430FR5969-SP
ADC Module
Functional
Incorrect conversion result in extended sample mode in some conditions
The ADC12 conversion result can be incorrect if the extended sample mode is selected (ADC12SHP = 0), ADC12VRSEL is set to 0, 2, 4, 6, 12, 14 (VR+ and VR- unbuffered), and the ADC sample time is less than 6 ADC clock cycles.
1) Use Pulse sample mode (ADC12SHP=1) if sample time less than 6 ADC clock cycles is needed;
OR
2) In extended sample mode (ADC12SHP = 0) increase the sample time to at least 6 ADC clock cycles;
OR
3) Use reference mode corresponding to ADC12VRSEL =1,3,5,7,9,13,15