SLAZ504AC January   2013  – May 2021 MSP430F67491

 

  1. 1Functional Advisories
  2. 2Preprogrammed Software Advisories
  3. 3Debug Only Advisories
  4. 4Fixed by Compiler Advisories
  5. 5Nomenclature, Package Symbolization, and Revision Identification
    1. 5.1 Device Nomenclature
    2. 5.2 Package Markings
      1.      PEU128
      2.      PZ100
    3. 5.3 Memory-Mapped Hardware Revision (TLV Structure)
  6. 6Advisory Descriptions
    1. 6.1  ADC39
    2. 6.2  ADC42
    3. 6.3  ADC69
    4. 6.4  AUXPMM1
    5. 6.5  AUXPMM2
    6. 6.6  BSL7
    7. 6.7  BSL14
    8. 6.8  COMP10
    9. 6.9  CPU21
    10. 6.10 CPU22
    11. 6.11 CPU36
    12. 6.12 CPU37
    13. 6.13 CPU40
    14. 6.14 CPU46
    15. 6.15 CPU47
    16. 6.16 DMA4
    17. 6.17 DMA7
    18. 6.18 DMA9
    19. 6.19 DMA10
    20. 6.20 EEM17
    21. 6.21 EEM19
    22. 6.22 EEM23
    23. 6.23 JTAG26
    24. 6.24 JTAG27
    25. 6.25 LCDB6
    26. 6.26 PMM11
    27. 6.27 PMM12
    28. 6.28 PMM14
    29. 6.29 PMM15
    30. 6.30 PMM18
    31. 6.31 PMM20
    32. 6.32 PMM26
    33. 6.33 PORT15
    34. 6.34 PORT19
    35. 6.35 PORT26
    36. 6.36 RTC8
    37. 6.37 SD3
    38. 6.38 SYS16
    39. 6.39 UCS11
    40. 6.40 USCI36
    41. 6.41 USCI37
    42. 6.42 USCI41
    43. 6.43 USCI42
    44. 6.44 USCI47
    45. 6.45 USCI50
  7. 7Revision History

6.27 PMM12

PMM Module

Category

Functional

Function

SMCLK comesup fast on exit from LPM3 and LPM4

Description

The DCO exceeds the programmed frequency of operationon exit from LPM3 and LPM4 for up to 6 us. When SMCLK is sourced by the DCO, it is not masked on exit from LPM3 or LPM4. Therefore, SMCLK exceeds the programmed frequency of operation on exit from LPM3 and LPM4 for up to 6 us. The increased frequency has the potential to change the expected timing behavior of peripherals that select SMCLK as the clock source.

Workaround

- Use XT2 as the SMCLK oscillator source instead of the DCO

or

- Do not disable the clock request bit for SMCLKREQEN in the Unified Clock System Control 8 Register (UCSCTL8). This means that all modules that depend on SMCLK to operate successfully should be halted or disabled before entering LPM3 or LPM4. If the increased frequency prevents the proper function of an affected module, wait 32, 48, 80 or 100 cycles for core voltage levels 0, 1, 2, or 3, respectively, before re-enabling the module. (for example,  __delay_cycles(100)