SLAZ504AC January   2013  – May 2021 MSP430F67491

 

  1. 1Functional Advisories
  2. 2Preprogrammed Software Advisories
  3. 3Debug Only Advisories
  4. 4Fixed by Compiler Advisories
  5. 5Nomenclature, Package Symbolization, and Revision Identification
    1. 5.1 Device Nomenclature
    2. 5.2 Package Markings
      1.      PEU128
      2.      PZ100
    3. 5.3 Memory-Mapped Hardware Revision (TLV Structure)
  6. 6Advisory Descriptions
    1. 6.1  ADC39
    2. 6.2  ADC42
    3. 6.3  ADC69
    4. 6.4  AUXPMM1
    5. 6.5  AUXPMM2
    6. 6.6  BSL7
    7. 6.7  BSL14
    8. 6.8  COMP10
    9. 6.9  CPU21
    10. 6.10 CPU22
    11. 6.11 CPU36
    12. 6.12 CPU37
    13. 6.13 CPU40
    14. 6.14 CPU46
    15. 6.15 CPU47
    16. 6.16 DMA4
    17. 6.17 DMA7
    18. 6.18 DMA9
    19. 6.19 DMA10
    20. 6.20 EEM17
    21. 6.21 EEM19
    22. 6.22 EEM23
    23. 6.23 JTAG26
    24. 6.24 JTAG27
    25. 6.25 LCDB6
    26. 6.26 PMM11
    27. 6.27 PMM12
    28. 6.28 PMM14
    29. 6.29 PMM15
    30. 6.30 PMM18
    31. 6.31 PMM20
    32. 6.32 PMM26
    33. 6.33 PORT15
    34. 6.34 PORT19
    35. 6.35 PORT26
    36. 6.36 RTC8
    37. 6.37 SD3
    38. 6.38 SYS16
    39. 6.39 UCS11
    40. 6.40 USCI36
    41. 6.41 USCI37
    42. 6.42 USCI41
    43. 6.43 USCI42
    44. 6.44 USCI47
    45. 6.45 USCI50
  7. 7Revision History

6.18 DMA9

DMA Module

Category

Functional

Function

DMA stops transferring bytes unexpectedly

Description

When the DMA is configured to transfer bytes from the eUSCI_A or eUSCI_B transmit or receive buffers, the transmit or receive triggers (TXIFG and RXIFG) may not be seen by the DMA module and the transfer of the bytes is missed. Once the first byte in a transfer sequence is missed, all the following bytes are missed as well. All eUSCI_A modes (UART, SPI, and IrDA) and all eUSCI_B modes (SPI and I2C) are affected.

Workaround

1) Use Interrupt Service Routines to transfer data to and from the eUSCI_A or eUSCI_B.
OR
2) When using DMA channel 0 for transferring data to and from the eUSCI_A or eUSCI_B, use DMA channel 2 (lower priority than DMA channel 0) to read the same register of the eUSCI_A or eUSCI_B  that DMA channel 0 is working with. Use the same USCI IFG (e.g. UCA0RXIFG) as trigger source for these both DMA channels.