SLAZ517AG March   2013  – August 2021 MSP430FR6989

 

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6.26 ESI2

ESI Module

Category

Functional

Function

TSM1 register corruption

Description

When CPU performs write operations to any ESI register during active TSM (Timing State Machine) sequence, the TSM1 register might be corrupted. The critical scenario is a CPU write access at the end of the TSM sequence.

Workaround

Gate ESI write accesses during TSM active phase by reading the TSM register pointer from ESIDEBUG2 to ensure TSM is in IDLE state (TSM_Index = 0).



__bic_SR_register(GIE);     // disable interrupts  important
                            // to not interrupt the SW gating

while (ESIDEBUG2_H != 0x00);// check TSM state pointer to 
                            // ensure IDLE state before 
                            // write access

ESICNT2 = 0x00000;          // example write to any ESI 
                            // register

__bis_SR_register(GIE);     // re-enable interrupts



Due to this workaround the device stays maximum 1 TSM sequence longer in Active mode.

The CPU access must not extend the Idle time of the TSM.
The gating should be used for each write operation or a sequence of ESI write accesses in a row.