SLAZ542T July   2013  – May 2021 MSP430F5234

 

  1. 1Functional Advisories
  2. 2Preprogrammed Software Advisories
  3. 3Debug Only Advisories
  4. 4Fixed by Compiler Advisories
  5. 5Nomenclature, Package Symbolization, and Revision Identification
    1. 5.1 Device Nomenclature
    2. 5.2 Package Markings
      1.      RGZ48
    3. 5.3 Memory-Mapped Hardware Revision (TLV Structure)
  6. 6Advisory Descriptions
    1. 6.1  BSL7
    2. 6.2  COMP10
    3. 6.3  CPU21
    4. 6.4  CPU22
    5. 6.5  CPU40
    6. 6.6  CPU47
    7. 6.7  DMA4
    8. 6.8  DMA7
    9. 6.9  DMA10
    10. 6.10 EEM17
    11. 6.11 EEM19
    12. 6.12 EEM21
    13. 6.13 EEM23
    14. 6.14 JTAG26
    15. 6.15 JTAG27
    16. 6.16 PMAP1
    17. 6.17 PMM9
    18. 6.18 PMM11
    19. 6.19 PMM12
    20. 6.20 PMM14
    21. 6.21 PMM15
    22. 6.22 PMM18
    23. 6.23 PMM20
    24. 6.24 PORT15
    25. 6.25 PORT19
    26. 6.26 PORT33
    27. 6.27 RTC3
    28. 6.28 RTC6
    29. 6.29 SYS12
    30. 6.30 SYS16
    31. 6.31 UCS7
    32. 6.32 UCS9
    33. 6.33 UCS11
    34. 6.34 USCI26
    35. 6.35 USCI34
    36. 6.36 USCI35
    37. 6.37 USCI39
    38. 6.38 USCI40
  7. 7Revision History

6.9 DMA10

DMA Module

Category

Functional

Function

DMA access may cause invalid module operation

Description

The peripheral modules MPY, CRC, USB, RF1A and FRAM controller in manual mode can stall the CPU by issuing wait states while in operation. If a DMA access to the module occurs while that module is issuing a wait state, the module may exhibit undefined behavior.

Workaround

Ensure that DMA accesses to the affected modules occur only when the modules are not in operation. For example with the MPY module, ensure that the MPY operation is completed before triggering a DMA access to the MPY module.