SLAZ547T July   2013  – May 2021 MSP430F5247

 

  1. 1Functional Advisories
  2. 2Preprogrammed Software Advisories
  3. 3Debug Only Advisories
  4. 4Fixed by Compiler Advisories
  5. 5Nomenclature, Package Symbolization, and Revision Identification
    1. 5.1 Device Nomenclature
    2. 5.2 Package Markings
      1.      YFF64
      2.      ZQE80
      3.      RGC64
    3. 5.3 Memory-Mapped Hardware Revision (TLV Structure)
  6. 6Advisory Descriptions
    1. 6.1  ADC39
    2. 6.2  ADC42
    3. 6.3  ADC69
    4. 6.4  BSL7
    5. 6.5  COMP10
    6. 6.6  CPU21
    7. 6.7  CPU22
    8. 6.8  CPU40
    9. 6.9  CPU47
    10. 6.10 DMA4
    11. 6.11 DMA7
    12. 6.12 DMA10
    13. 6.13 EEM17
    14. 6.14 EEM19
    15. 6.15 EEM21
    16. 6.16 EEM23
    17. 6.17 JTAG26
    18. 6.18 JTAG27
    19. 6.19 PMAP1
    20. 6.20 PMM9
    21. 6.21 PMM11
    22. 6.22 PMM12
    23. 6.23 PMM14
    24. 6.24 PMM15
    25. 6.25 PMM18
    26. 6.26 PMM20
    27. 6.27 PORT15
    28. 6.28 PORT19
    29. 6.29 PORT33
    30. 6.30 RTC3
    31. 6.31 RTC6
    32. 6.32 SYS12
    33. 6.33 SYS16
    34. 6.34 UCS7
    35. 6.35 UCS9
    36. 6.36 UCS11
    37. 6.37 USCI26
    38. 6.38 USCI34
    39. 6.39 USCI35
    40. 6.40 USCI39
    41. 6.41 USCI40
  7. 7Revision History

6.12 DMA10

DMA Module

Category

Functional

Function

DMA access may cause invalid module operation

Description

The peripheral modules MPY, CRC, USB, RF1A and FRAM controller in manual mode can stall the CPU by issuing wait states while in operation. If a DMA access to the module occurs while that module is issuing a wait state, the module may exhibit undefined behavior.

Workaround

Ensure that DMA accesses to the affected modules occur only when the modules are not in operation. For example with the MPY module, ensure that the MPY operation is completed before triggering a DMA access to the MPY module.