SLAZ548T July   2013  – May 2021 MSP430F5249

 

  1. 1Functional Advisories
  2. 2Preprogrammed Software Advisories
  3. 3Debug Only Advisories
  4. 4Fixed by Compiler Advisories
  5. 5Nomenclature, Package Symbolization, and Revision Identification
    1. 5.1 Device Nomenclature
    2. 5.2 Package Markings
      1.      YFF64
      2.      ZQE80
      3.      RGC64
    3. 5.3 Memory-Mapped Hardware Revision (TLV Structure)
  6. 6Advisory Descriptions
    1. 6.1  ADC39
    2. 6.2  ADC42
    3. 6.3  ADC69
    4. 6.4  BSL7
    5. 6.5  COMP10
    6. 6.6  CPU21
    7. 6.7  CPU22
    8. 6.8  CPU40
    9. 6.9  CPU47
    10. 6.10 DMA4
    11. 6.11 DMA7
    12. 6.12 DMA10
    13. 6.13 EEM17
    14. 6.14 EEM19
    15. 6.15 EEM21
    16. 6.16 EEM23
    17. 6.17 JTAG26
    18. 6.18 JTAG27
    19. 6.19 PMAP1
    20. 6.20 PMM9
    21. 6.21 PMM11
    22. 6.22 PMM12
    23. 6.23 PMM14
    24. 6.24 PMM15
    25. 6.25 PMM18
    26. 6.26 PMM20
    27. 6.27 PORT15
    28. 6.28 PORT19
    29. 6.29 PORT33
    30. 6.30 RTC3
    31. 6.31 RTC6
    32. 6.32 SYS12
    33. 6.33 SYS16
    34. 6.34 UCS7
    35. 6.35 UCS9
    36. 6.36 UCS11
    37. 6.37 USCI26
    38. 6.38 USCI34
    39. 6.39 USCI35
    40. 6.40 USCI39
    41. 6.41 USCI40
  7. 7Revision History

6.8 CPU40

CPU Module

Category

Compiler-Fixed

Function

PC is corrupted when executing jump/conditional jump instruction that is followed by instruction with PC as destination register or a data section

Description

If the value at the memory location immediately following a jump/conditional jump instruction is 0X40h or 0X50h (where X = don't care), which could either be an instruction opcode (for instructions like RRCM, RRAM, RLAM, RRUM) with PC as destination register or a data section (const data in flash memory or data variable in
RAM), then the PC value is auto-incremented by 2 after the jump instruction is executed; therefore, branching to a wrong address location in code and leading to wrong program execution.

For example, a conditional jump instruction followed by data section (0140h).

@0x8012   Loop     DEC.W  R6
@0x8014            DEC.W  R7
@0x8016            JNZ    Loop
@0x8018   Value1   DW     0140h

Workaround

In assembly, insert a NOP between the jump/conditional jump instruction and program code with instruction that contains PC as destination register or the data section.

Refer to the table below for compiler-specific fix implementation information.

IDE/Compiler Version Number Notes
IAR Embedded Workbench IAR EW430 v5.51 or later For the command line version add the following information Compiler: --hw_workaround=CPU40 Assembler:-v1
TI MSP430 Compiler Tools (Code Composer Studio) v4.0.x or later User is required to add the compiler or assembler flag option below. --silicon_errata=CPU40
MSP430 GNU Compiler (MSP430-GCC) Not affected