SLAZ552W September   2014  – May 2021 MSP430FR4131

 

  1. 1Functional Advisories
  2. 2Preprogrammed Software Advisories
  3. 3Debug Only Advisories
  4. 4Fixed by Compiler Advisories
  5. 5Nomenclature, Package Symbolization, and Revision Identification
    1. 5.1 Device Nomenclature
    2. 5.2 Package Markings
      1.      DGG48
      2.      DGG56
      3.      PM64
    3. 5.3 Memory-Mapped Hardware Revision (TLV Structure)
  6. 6Advisory Descriptions
    1. 6.1  ADC39
    2. 6.2  ADC50
    3. 6.3  ADC63
    4. 6.4  CPU21
    5. 6.5  CPU22
    6. 6.6  CPU40
    7. 6.7  CPU46
    8. 6.8  CS11
    9. 6.9  CS13
    10. 6.10 EEM23
    11. 6.11 EEM28
    12. 6.12 EEM30
    13. 6.13 GC1
    14. 6.14 GC4
    15. 6.15 GC5
    16. 6.16 PMM32
    17. 6.17 PORT28
    18. 6.18 RTC15
    19. 6.19 SYS23
    20. 6.20 USCI41
    21. 6.21 USCI42
    22. 6.22 USCI45
    23. 6.23 USCI47
    24. 6.24 USCI50
  7. 7Revision History

6.22 USCI45

USCI Module

Category

Functional

Function

Unexpected SPI clock stretching possible when UCxCLK is asynchronous to MCLK

Description

In rare cases, during SPI communication, the clock high phase of the first data bit may be stretched significantly. The SPI operation completes as expected with no data loss. This issue only occurs when the USCI SPI module clock (UCxCLK) is asynchronous to the system clock (MCLK).

Workaround

Ensure that the USCI SPI module clock (UCxCLK) and the CPU clock (MCLK) are synchronous to each other.