SLAZ552W September 2014 – May 2021 MSP430FR4131
ADC Module
Functional
Erroneous ADC results in extended sample mode
If the extended sample mode is selected (ADCSHP = 0) and the ADCCLK is asynchronous to the SHI signal, the ADC may generate erroneous results.
1) Use the pulse sample mode (ADCSHP=1)
OR
2) Use a synchronous clock for ADC and the SHI signal. For example, if SMCLK is used to source Timer to trigger SHI, ADCCLK should also be sourced by SMCLK.