SLAZ591V January   2014  – May 2021 MSP430F6776A

 

  1. 1Functional Advisories
  2. 2Preprogrammed Software Advisories
  3. 3Debug Only Advisories
  4. 4Fixed by Compiler Advisories
  5. 5Nomenclature, Package Symbolization, and Revision Identification
    1. 5.1 Device Nomenclature
    2. 5.2 Package Markings
      1.      PEU128
      2.      PZ100
    3. 5.3 Memory-Mapped Hardware Revision (TLV Structure)
  6. 6Advisory Descriptions
    1. 6.1  ADC39
    2. 6.2  ADC42
    3. 6.3  ADC69
    4. 6.4  AES1
    5. 6.5  AUXPMM2
    6. 6.6  BSL7
    7. 6.7  BSL14
    8. 6.8  COMP10
    9. 6.9  CPU21
    10. 6.10 CPU22
    11. 6.11 CPU36
    12. 6.12 CPU37
    13. 6.13 CPU40
    14. 6.14 CPU46
    15. 6.15 CPU47
    16. 6.16 DMA4
    17. 6.17 DMA7
    18. 6.18 DMA9
    19. 6.19 DMA10
    20. 6.20 EEM17
    21. 6.21 EEM19
    22. 6.22 EEM23
    23. 6.23 JTAG26
    24. 6.24 JTAG27
    25. 6.25 LCDB6
    26. 6.26 PMM11
    27. 6.27 PMM12
    28. 6.28 PMM14
    29. 6.29 PMM15
    30. 6.30 PMM18
    31. 6.31 PMM20
    32. 6.32 PMM26
    33. 6.33 PORT15
    34. 6.34 PORT19
    35. 6.35 PORT26
    36. 6.36 SD3
    37. 6.37 SYS16
    38. 6.38 UCS11
    39. 6.39 USCI36
    40. 6.40 USCI37
    41. 6.41 USCI41
    42. 6.42 USCI42
    43. 6.43 USCI47
    44. 6.44 USCI50
  7. 7Revision History

6.28 PMM14

PMM Module

Category

Functional

Function

Increasing the core level when SVS/SVM low side is configured in full-performance mode causes device reset

Description

When the SVS/SVM low side is configured in full performance mode (SVSMLCTL.SVSLFP = 1), the setting time delay for the SVS comparators is ~2us. When increasing the core level in full-performance mode; the core voltage does not settle to the new level before the settling time delay of the SVS/SVM comparator expires. This results in a device reset.

Workaround

When increasing the core level; enable the SVS/SVM low side in normal mode (SVSMLCTL.SVSLFP=0). This provides a settling time delay of approximately 150us allowing the core sufficient time to increase to the expected voltage before the delay expires.