SLAZ606V August   2014  – May 2021 MSP430F67641

 

  1.   1
  2.   2
  3.   3
  4.   4
  5.   5
    1.     6
    2.     7
      1.      8
      2.      9
    3.     10
  6.   11
    1.     12
    2.     13
    3.     14
    4.     15
    5.     16
    6.     17
    7.     18
    8.     19
    9.     20
    10.     21
    11.     22
    12.     23
    13.     24
    14.     25
    15.     26
    16.     27
    17.     28
    18.     29
    19.     30
    20.     31
    21.     32
    22.     33
    23.     34
    24.     35
    25.     36
    26.     37
    27.     38
    28.     39
    29.     40
    30.     41
    31.     42
    32.     43
    33.     44
    34.     45
    35.     46
    36.     47
    37.     48
    38.     49
    39.     50
    40.     51
    41.     52
    42.     53
    43.     54
  7.   55

6.32 PMM20

PMM Module

Category

Functional

Function

Unexpected SVSL/SVML event during wakeup from LPM2/3/4 in fast wakeup mode

Description

If PMM low side is configured to operate in fast wakeup mode, during wakeup from LPM2/3/4 the internal VCORE voltage can experience voltage drop below the corresponding SVSL and SVML threshold (recommendation according to User's Guide) leading to an unexpected SVSL/SVML event. Depending on PMM configuration, this event triggers a POR or an interrupt.

Note: As soon the SVSL or the SVML is enabled in Normal performance mode the device is in slow wakeup mode and this erratum does not apply. In addition, this erratum has sporadic characteristic due to an internal asynchronous circuit. The drop of Vcore does not have an impact on specified device performance.

Workaround

If SVSL or SVML is required for application (to observe external disruptive events at Vcore pin) the slow wakeup mode has to be used to avoid unexpected SVSL/SVML events. This is achieved if the SVSL or the SVML is configured in "Normal" performance mode (not disabled and not in "Full" Performance Mode).