SLAZ620AA August   2014  – August 2021 MSP430FR6977

 

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6.34 PMM29

PMM Module

Category

Functional

Function

Device may enter lockup state during wake-up from LPM2, LPM3, and LPM4

Description

In rare cases, the device may enter lockup state during wake up from LPM2, LPM3, or LPM4. The device will remain in lockup state, unable to respond to interrupts or continue application execution, until a BOR reset occurs.

LPM0, LPM1, LPM3.5 and LPM4.5 are not affected by this behavior.

Workaround

1) Use LPM0 or LPM1. See device datasheet for details on wake up time and power consumption.

OR

2) Use LPM3.5 or LPM4.5 Note that only RTC or GPIO can wake from LPM3.5/4.5 and see device datasheet for details on wake up time and power consumption. When using LPM3.5/4.5 the Compute Through Power Loss (CTPL) Utility APIs, found in the FRAM Utilities download, can be used to configure device behavior prior to LPM entry and on wake-up.

OR

3) At the beginning of code, clear the FRLPMPWR bit in the GCCTL0 register, as shown below: 


// PMM29 workaround. 
FRCTL0 = FRCTLPW;
GCCTL0 = FRPWR; //clear FRLPMPWR while keeping FRPWR set
FRCTL0_H = 0; //re-lock FRCTL
// End PMM29 workaround


This adds additional latency when waking from LPM to enter the ISR. To calculate the new wake up time with FRLPMPWR bit cleared, take the wake-up time for the low power mode used and add the twake-up FRAM value specified in the datasheet.
E.g. twake-up workaround = twake-up LPM3 + twake-up FRAM

Note: For workaround (3), if the WDT triggers a PUC reset during LPM2, 3 or 4 the FRLPMPWR bit will be re-set before the wake-up occurs, meaning the workaround will not be effective and the part could still enter lock-up state. In this case it is recommended to configure the WDT to interval timer mode and trigger a PUC reset via WDT PW violation.