SLAZ651S February 2015 – May 2021 MSP430F6730A
USCI Module
Functional
Reading RXBUF during an active I2C communication might result in unintended bus stalls.
The falling edge of SCL bus line is used to set an internal RXBUF-written flag register, which is used to detect a potential RXBUF overflow. If this flag is cleared with a read access from the RXBUF register during a falling edge of SCL, the clear condition might be missed. This could result in an I2C bus stall at the next received byte.
(1) Execute two consecutive reads of RXBUF, if tSCL > 4 x tMCLK.
or
(2) Provoke an I2C bus stall before reading RXBUF. A bus stall can be verified by checking if the clock line low status indicator bit UCSCLLOW is set for at least three USCI bit clock cycles i.e. 3 x tBitClock.