SLAZ662S March   2015  – May 2021 MSP430FR2632

 

  1. 1Functional Advisories
  2. 2Preprogrammed Software Advisories
  3. 3Debug Only Advisories
  4. 4Fixed by Compiler Advisories
  5. 5Nomenclature, Package Symbolization, and Revision Identification
    1. 5.1 Device Nomenclature
    2. 5.2 Package Markings
      1.      YQW24
      2.      RGE24
    3. 5.3 Memory-Mapped Hardware Revision (TLV Structure)
  6. 6Advisory Descriptions
    1. 6.1  ADC50
    2. 6.2  ADC63
    3. 6.3  BSL18
    4. 6.4  CPU21
    5. 6.5  CPU22
    6. 6.6  CPU40
    7. 6.7  CPU46
    8. 6.8  CS13
    9. 6.9  EEM23
    10. 6.10 GC4
    11. 6.11 GC5
    12. 6.12 PMM32
    13. 6.13 PORT28
    14. 6.14 RTC15
    15. 6.15 USCI42
    16. 6.16 USCI45
    17. 6.17 USCI47
    18. 6.18 USCI50
  7. 7Revision History

6.10 GC4

GC Module

Category

Functional

Function

Unexpected PUC is triggered

Description

During execution from FRAM a non-existent uncorrectable bit error can be detected and trigger a PUC if the uncorrectable bit error detection flag is set (GCCTL0.UBDRSTEN = 1). This behavior appears only if:

(1) MCLK is sourced from DCO frequency of 16 MHz

OR

(2) MCLK is sourced by external high frequency clock above 12 MHz at pin HFXIN

OR

(3) MCLK is sourced by High-Frequency crystals (HFXT) above 12 MHz.  

This PUC will not be recognized by the SYSRSTIV register (SYSRSTIV = 0x00).
A PUC RESET will be executed with not defined reset source.
Also the corresponding bit error detection flag is not set  (GCCTL1.UBDIFG = 0).

Workaround

1. Check the reset source for SYSRSTIV = 0 and ignore the reset.

OR

2. Set GCCTL0.UBDRSTEN = 0 to prevent unexpected PUC.

OR

3. Set the MCLK to maximum 12MHz to leverage the uncorrectable bit error PUC feature.