SLAZ703M March   2017  – October 2021 MSP430FR2100

 

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6.8 CS14

CS Module

Category

Functional

Function

TLV values for 16MHz calibration are shifted beyond datasheet error limits

Description

During setting DCO frequency to 16MHz, 16MHz DCO tap settings value inside of TLV is used as the CSCTL0 setting. In this case after FLL locked, DCO 16MHz frequency can shift outside of datasheet specification of +/- 1% at 25C for a maximum time of 60ms. After the maximum time of 60ms, DCO frequency error will settle back to DCO FLL lock frequency of 16 MHz +/- 1%  at 25C specified in device data sheet

Workaround

1. After setting the DCO frequency to 16MHz, set a 300us delay in software, then poll the FLL locked status bits in CSCTL7 Register. Once the FLL is locked, the DCO frequency will match the device data sheet specifications.
OR
2. During first power on of MCU:
- set DCO frequency to 16MHz,
- set a 300us delay in software,
- poll FLL locked status bits in CSCTL7 until FLL lock
- store DCO tap settings by reading CSCTL0 register value and write to FRAM
The stored DCO tap settings can then be loaded into CSCTL0 when setting the DCO to 16MHz in order to reduce FLL lock duration. This value will be used in lieu of TLV values.