SLAZ730B January   2019  – August 2021 MSP430FR5043

 

  1. 1Functional Advisories
  2. 2Preprogrammed Software Advisories
  3. 3Debug Only Advisories
  4. 4Fixed by Compiler Advisories
  5. 5Nomenclature, Package Symbolization, and Revision Identification
    1. 5.1 Device Nomenclature
    2. 5.2 Package Markings
      1.      PM64
      2.      RGC64
    3. 5.3 Memory-Mapped Hardware Revision (TLV Structure)
  6. 6Advisory Descriptions
    1. 6.1  ADC42
    2. 6.2  ADC65
    3. 6.3  ADC68
    4. 6.4  ADC69
    5. 6.5  ADC70
    6. 6.6  ADC71
    7. 6.7  CPU21
    8. 6.8  CPU22
    9. 6.9  CPU40
    10. 6.10 CPU46
    11. 6.11 CPU47
    12. 6.12 CS12
    13. 6.13 PMM31
    14. 6.14 PMM32
    15. 6.15 RTC12
    16. 6.16 TB25
    17. 6.17 USCI42
    18. 6.18 USCI45
    19. 6.19 USCI47
    20. 6.20 USCI50
  7. 7Revision History

6.4 ADC69

ADC Module

Category

Functional

Function

ADC stops operating if ADC clock source is changed from SMCLK to another source while SMCLKOFF = 1.

Description

When SMCLK is used as the clock source for the ADC (ADC12CTL1.ADC12SSELx = 11) and CSCTL4.SMCLKOFF = 1, the ADC will stop operating if the ADC clock source is changed by user software (e.g. in the ISR) from SMCLK to a different clock source. This issue appears only for the ADC12CTL1.ADC12DIVx settings /3/5/7. The hang state can be recovered by PUC/POR/BOR/Power cycle.

Workaround

1. Set CSCTL4.SMCLKOFF = 0 before switch ADC clock source.

OR

2. Only use ADC12CTL1.ADC12DIVx as /1, /2, /4, /6, /8