SLAZ730B January   2019  – August 2021 MSP430FR5043

 

  1. 1Functional Advisories
  2. 2Preprogrammed Software Advisories
  3. 3Debug Only Advisories
  4. 4Fixed by Compiler Advisories
  5. 5Nomenclature, Package Symbolization, and Revision Identification
    1. 5.1 Device Nomenclature
    2. 5.2 Package Markings
      1.      PM64
      2.      RGC64
    3. 5.3 Memory-Mapped Hardware Revision (TLV Structure)
  6. 6Advisory Descriptions
    1. 6.1  ADC42
    2. 6.2  ADC65
    3. 6.3  ADC68
    4. 6.4  ADC69
    5. 6.5  ADC70
    6. 6.6  ADC71
    7. 6.7  CPU21
    8. 6.8  CPU22
    9. 6.9  CPU40
    10. 6.10 CPU46
    11. 6.11 CPU47
    12. 6.12 CS12
    13. 6.13 PMM31
    14. 6.14 PMM32
    15. 6.15 RTC12
    16. 6.16 TB25
    17. 6.17 USCI42
    18. 6.18 USCI45
    19. 6.19 USCI47
    20. 6.20 USCI50
  7. 7Revision History

6.16 TB25

TB Module

Category

Functional

Function

In up mode, TBxCCRn value is immediately transferred to TBxCLn when TBxCCTLn.CLLD bits are set or 0x01 or 0x10

Description

IF Timer B is configured for Up mode,
AND
the compare latch load event (TBxCCTLn.CLLD bits) setting is configured to update TBxCCRn  when TBxR reaches 0,
THEN
TBxCCRn will update immediately instead of the described condition.

This is contrary to the user guide description of  TBxCCTLn.CLLD = 0x01 or 0x10 modes.

Workaround

If user needs to update TBxCCRn value when TBxR counts to 0 in Timer B up mode:

1. Set TBxCCTLn. CLLD = 0x00
2. Enable the Timer B interrupt (TBIE) in TBxCTL
3. Update TBxCCRn value within interrupt routine.

Timer B Interrupt would need to be serviced in a timely manner to mitigate disruption or unintended timer output if an output mode is used.