SLAZ730B January   2019  – August 2021 MSP430FR5043

 

  1. 1Functional Advisories
  2. 2Preprogrammed Software Advisories
  3. 3Debug Only Advisories
  4. 4Fixed by Compiler Advisories
  5. 5Nomenclature, Package Symbolization, and Revision Identification
    1. 5.1 Device Nomenclature
    2. 5.2 Package Markings
      1.      PM64
      2.      RGC64
    3. 5.3 Memory-Mapped Hardware Revision (TLV Structure)
  6. 6Advisory Descriptions
    1. 6.1  ADC42
    2. 6.2  ADC65
    3. 6.3  ADC68
    4. 6.4  ADC69
    5. 6.5  ADC70
    6. 6.6  ADC71
    7. 6.7  CPU21
    8. 6.8  CPU22
    9. 6.9  CPU40
    10. 6.10 CPU46
    11. 6.11 CPU47
    12. 6.12 CS12
    13. 6.13 PMM31
    14. 6.14 PMM32
    15. 6.15 RTC12
    16. 6.16 TB25
    17. 6.17 USCI42
    18. 6.18 USCI45
    19. 6.19 USCI47
    20. 6.20 USCI50
  7. 7Revision History

6.18 USCI45

USCI Module

Category

Functional

Function

Unexpected SPI clock stretching possible when UCxCLK is asynchronous to MCLK

Description

In rare cases, during SPI communication, the clock high phase of the first data bit may be stretched significantly and sometimes one byte data may be also missing. This issue only occurs when the USCI SPI module clock (UCxCLK) is asynchronous to the system clock (MCLK).

Workaround

Ensure that the USCI SPI module clock (UCxCLK) and the CPU clock (MCLK) are synchronous to each other.