SLAZ733B February   2020  – August 2021 MSP430FR6007

 

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6.25 USCI52

USCI Module

Category

Functional

Function

Interrupt Flag polling can cause unrpedictable behavior if eUSCI is running with different clock then CPU

Description

If the interrupt flags e.g. UCAIFG of the eUSCI are polled via the CPU during a while loop or during the following assembly instruction the CPU behavior can become unpredictable when the corresponding interrupt flag is set asynchronously during the execution of the bit instruction. The corresponding CPU flags used by the conditional jump can become unstable causing unpredictable CPU execution.  

CHECK_FLAG
           BIT.W  #8,&UCAxIFG
           JEQ      CHECK_FLAG

Workaround

Buffer the interrupt flag which should be polled, to a CPU internal register e.g. R15 and use this register for the decision (bit + jeq).
The bit of interest remains stable during the CPU decision because the value is settled in the CPU internal register.
In C, declaring the buffer variable as volatile avoids compiler optimizations that may result in the assembly code above.

Workaround in C:
volatile unsigned short flag;
do
{
flag = UCA0IG;
}while ((flag & UCRXIFG) == 0x00);

Workaround in asm:
           PUSH    R15
loop:
           MOV.W  &UCAxIFG, R15    
           BIT.W    #8,R15
           JEQ       loop
           POP      R15