SLAZ755 May   2024 MSPM0L1228 , MSPM0L2228

ADVANCE INFORMATION  

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Functional Advisories
  5. 2Preprogrammed Software Advisories
  6. 3Debug Only Advisories
  7. 4Fixed by Compiler Advisories
  8. 5Device Nomenclature
    1. 5.1 Device Symbolization and Revision Identification
  9. 6Advisory Descriptions
    1. 6.1  ADC_ERR_02
    2. 6.2  ADC_ERR_06
    3. 6.3  COMP_ERR_03
    4. 6.4  DEBUGSS_ERR_01
    5. 6.5  I2C_ERR_01
    6. 6.6  I2C_ERR_03
    7. 6.7  I2C_ERR_04
    8. 6.8  LCD_ERR_01
    9. 6.9  LFSS_ERR_01
    10. 6.10 LFSS_ERR_02
    11. 6.11 RTC_A_ERR_01
    12. 6.12 SRAM_ERR_01
    13. 6.13 SPI_ERR_03
    14. 6.14 SYSOSC_ERR_01
    15. 6.15 UART_ERR_02
    16. 6.16 VREF_ERR_02
  10. 7Revision History

6.13 SPI_ERR_03

When configured as peripheral for a multi-peripheral application, received data will have a right shift on communications after the first.

Revisions Affected

Rev X

Details

When the MCU is set as peripheral:

In multi-peripheral scenario, SPI controller first communicates with peripheral0 and then communicates with peripheral1. After finishing communication with peripheral1, the controller again communicates with peripheral0. During the second communication with peripheral0, received data of peripheral0 will have a right shift in the first frame.

The peripheral0 is getting data as 0x3B when the controller sent data 0x76.

Workaround

To support multi peripheral scenario, CSCLR needs to be enabled at peripheral end to reset the RX and TX bit counters.