SLAZ758 November   2024 MSPM0G3519

 

  1.   1
  2.   Abstract
  3. 1Functional Advisories
  4. 2Preprogrammed Software Advisories
  5. 3Debug Only Advisories
  6. 4Fixed by Compiler Advisories
  7. 5Device Nomenclature
    1. 5.1 Device Symbolization and Revision Identification
  8. 6Advisory Descriptions
    1. 6.1  ADC_ERR_05
    2. 6.2  ADC_ERR_06
    3. 6.3  CPU_ERR_01
    4. 6.4  FLASH_ERR_01
    5. 6.5  I2C_ERR_05
    6. 6.6  PMCU_ERR_07
    7. 6.7  PMCU_ERR_10
    8. 6.8  SPI_ERR_02
    9. 6.9  SPI_ERR_04
    10. 6.10 SPI_ERR_05
    11. 6.11 SRAM_ERR_01
    12. 6.12 SYSOSC_ERR_01
    13. 6.13 SYSOSC_ERR_02
    14. 6.14 TIMER_ERR_06
    15. 6.15 UART_ERR_01
    16. 6.16 UART_ERR_02
  9. 7Trademarks
  10. 8Revision History

6.12 SYSOSC_ERR_01

SYSOSC Module

Category

Functional

Function

MFCLK drift when using SYSOSC FCL together with STOP1 mode

Description

If MFCLK is enabled AND SYSOSC is using the frequency correction loop (FCL) mode AND the STOP1 low power operating mode is used, Then the MFCLK may drift by two cycles when SYSOSC shifts from 4MHz back to 32MHz (either upon exit from STOP1 to RUN mode or upon an asynchronous fast clock request that forces SYSOSC to 32MHz).

Workaround


Use STOP0 mode instead of STOP1 mode. There is no MFCLK drift when STOP0 mode is used.

OR

Do not use SYSOSC in the FCL mode (leave FCL disabled) when using STOP1.