SLIS132A October   2008  – March 2015 TPS55065-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Dissipation Ratings
    6. 6.6 Electrical Characteristics
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Switched-Mode Input/Output Terminals (L1, L2)
      2. 7.3.2  Supply Terminal (Vdriver)
      3. 7.3.3  Internal Supply Decoupling Terminal (Vlogic)
      4. 7.3.4  Input Voltage Monitoring Terminal (AIN)
      5. 7.3.5  Input Undervoltage Alarm Terminal (AOUT)
      6. 7.3.6  Reset Delay Timer Terminal (REST)
      7. 7.3.7  Reset Terminal (RESET)
      8. 7.3.8  Main Regulator Output Terminal (VOUT)
      9. 7.3.9  Low-Power-Mode Terminal (CLP)
      10. 7.3.10 Switch-Output Terminal (5Vg)
      11. 7.3.11 5Vg-Enable Terminal (5Vg_ENABLE)
      12. 7.3.12 Slew-Rate Control Terminals (SCR0, SCR1)
      13. 7.3.13 Modulator Frequency Setting (Terminal Rmod)
      14. 7.3.14 Ground Terminal (PGND)
      15. 7.3.15 Enable Terminal (ENABLE)
      16. 7.3.16 Bootstrap Terminals (CBOOT1 and CBOOT2)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Clock Modulator
      2. 7.4.2 Buck/Boost Transitioning
      3. 7.4.3 Buck SMPS
      4. 7.4.4 Boost SMPS
      5. 7.4.5 Extension of the Input Voltage Range on V(driver)
      6. 7.4.6 Low-Power Mode
      7. 7.4.7 Temperature and Short-Circuit Protection
      8. 7.4.8 Switch Output Terminal (5Vg) Current Limitation
      9. 7.4.9 Soft Start
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Buck Mode
        2. 8.2.2.2 Boost Mode
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Inductor
      2. 10.1.2 Filter Capacitors
      3. 10.1.3 Traces and Ground Plane
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TPS55065 can be operated in a buck boost configuration with voltage mode control. The device is capable of monitoring the output as well as the input supply rail. The device also offers a frequency modulation scheme for minimizing EMI. The slew rate is set using the SCR0 and the SCR1 terminals. The average converter efficiency varies with the different slew rate controls of the Q1 switching FET. These variations are demonstrated using this design example at an input voltage of 11 V and 17 V.

8.2 Typical Application

TPS55065-Q1 app_schematic_lis132.gif
A. To minimize voltage ripple on the output due to transients, it is recommended to use a low-ESR capacitor on the VOUT line.
B. The L and C component values are system application dependent for EMI consideration.
Figure 19. Application Schematic

NOTE

When this attachment method is not implemented correctly, this product may operate inefficiently. Power dissipation capability may be adversely affected when the device is incorrectly mounted onto the circuit board.

8.2.1 Design Requirements

For this design example, use the parameters listed in Table 4 as the input parameters.

Table 4. Design Parameters

DESIGN PARAMETERS VALUE
Input voltage V(driver) 11 V to 18 V
Output current (maximum) 500 mA

Four different SCRx settings will be used to analyze the difference in converter efficiency with variations in slew rate (see Figure 20). The Buck equations mentioned in Buck Mode will be used to calculate the rest of the design parameters.

8.2.2 Detailed Design Procedure

8.2.2.1 Buck Mode

  • Select inductor ripple current ΔIL: for example, ΔIL = 0.2 × IOUT
  • Calculate inductor L
    • Equation 4. TPS55065-Q1 eq01_slis132.gif

    where

    • Inductor peak current
      • Equation 5. TPS55065-Q1 eq02_slis132.gif
    • Output voltage ripple
      • Equation 6. TPS55065-Q1 eq03_slis132.gif

      Usually, the first term is dominant.

      Equation 7. TPS55065-Q1 eq04_slis132.gif

    Using the previous equations, with Vin (maximum) as 18 V, Vout as 5 V, fSW as 440 kHz, and Inductor ripple current of 0.1 A, the inductance is calculated to be 82.1 µH with inductor peak current as 0.55 A.

    8.2.2.2 Boost Mode

    • Select inductor ripple current ΔIL: for example ΔIL = 0.2 × IIN
    • Calculate inductor L
      • Equation 8. TPS55065-Q1 eq05_slis132.gif

      where

      • Inductor peak current
        • Equation 9. TPS55065-Q1 eq06_slis132.gif
      • Output voltage ripple
        • Equation 10. TPS55065-Q1 eq07_slis132.gif

      8.2.3 Application Curve

      TPS55065-Q1 g_effic_io_lis132.gif
      Figure 20. Converter Efficiency