SLIS132A October   2008  – March 2015 TPS55065-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Dissipation Ratings
    6. 6.6 Electrical Characteristics
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Switched-Mode Input/Output Terminals (L1, L2)
      2. 7.3.2  Supply Terminal (Vdriver)
      3. 7.3.3  Internal Supply Decoupling Terminal (Vlogic)
      4. 7.3.4  Input Voltage Monitoring Terminal (AIN)
      5. 7.3.5  Input Undervoltage Alarm Terminal (AOUT)
      6. 7.3.6  Reset Delay Timer Terminal (REST)
      7. 7.3.7  Reset Terminal (RESET)
      8. 7.3.8  Main Regulator Output Terminal (VOUT)
      9. 7.3.9  Low-Power-Mode Terminal (CLP)
      10. 7.3.10 Switch-Output Terminal (5Vg)
      11. 7.3.11 5Vg-Enable Terminal (5Vg_ENABLE)
      12. 7.3.12 Slew-Rate Control Terminals (SCR0, SCR1)
      13. 7.3.13 Modulator Frequency Setting (Terminal Rmod)
      14. 7.3.14 Ground Terminal (PGND)
      15. 7.3.15 Enable Terminal (ENABLE)
      16. 7.3.16 Bootstrap Terminals (CBOOT1 and CBOOT2)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Clock Modulator
      2. 7.4.2 Buck/Boost Transitioning
      3. 7.4.3 Buck SMPS
      4. 7.4.4 Boost SMPS
      5. 7.4.5 Extension of the Input Voltage Range on V(driver)
      6. 7.4.6 Low-Power Mode
      7. 7.4.7 Temperature and Short-Circuit Protection
      8. 7.4.8 Switch Output Terminal (5Vg) Current Limitation
      9. 7.4.9 Soft Start
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Buck Mode
        2. 8.2.2.2 Boost Mode
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Inductor
      2. 10.1.2 Filter Capacitors
      3. 10.1.3 Traces and Ground Plane
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

10 Layout

10.1 Layout Guidelines

The following guidelines are recommended for PCB layout of the TPS55065 device.

10.1.1 Inductor

Use a low-EMI inductor with a ferrite-type closed core. Other types of inductors may be used; however, they must have low-EMI characteristics and be located away from the low-power traces and components in the circuit.

10.1.2 Filter Capacitors

Input ceramic filter capacitors should be located in the close proximity of the Vdriver terminal. Surface-mount capacitors are recommended to minimize lead length and reduce noise coupling.

10.1.3 Traces and Ground Plane

All power (high-current) traces should be thick and as short as possible. The inductor and output capacitors should be as close to each other as possible. This reduces EMI radiated by the power traces due to high switching currents.

In a two-sided PCB, it is recommended to have ground planes on both sides of the PCB to help reduce noise and ground-loop errors. The ground connection for the input and output capacitors and IC ground should be connected to this ground plane.

In a multilayer PCB, the ground plane is used to separate the power plane (where high switching currents and components are placed) from the signal plane (where the feedback trace and components are) for improved performance.

Also, arrange the components such that the switching-current loops curl in the same direction. Place the high-current components such that during conduction, the current path is in the same direction. This prevents magnetic field reversal caused by the traces between the two half-cycles, helping to reduce radiated EMI.

10.2 Layout Example

TPS55065-Q1 layout_top_slis132.gifFigure 21. Top Layer
TPS55065-Q1 layout_bottom_slis132.gifFigure 22. Bottom Layer

To maximize the efficiency of this package for application on a single-layer or multilayer PCB, certain guidelines must be followed when laying out this device on the PCB.

The following information is to be used as a guideline only.

For further information see the PowerPAD Thermally Enhanced Package technical brief (SLMA002).

The following are guidelines for mounting the PowerPAD™ IC on a multilayer PCB with a ground plane.

TPS55065-Q1 m0026-01.gifFigure 23. Package and PCB Land Configuration for a Multilayer PCB
TPS55065-Q1 m0027-01.gifFigure 24. Multilayer Board (Side View)

In a multilayer board application, the thermal vias are the primary method of heat transfer from the package thermal pad to the internal ground plane.

The efficiency of this method depends on several factors (die area, number of thermal vias, thickness of copper, and so forth). See the PowerPAD Thermally Enhanced Package technical brief (SLMA002).

TPS55065-Q1 m0028-01.gifFigure 25. Land Configuration for Single-Layer PCB

Layout recommendation is to use as much copper area for the power-management section of a single-layer board as possible. In a single-layer board application, the thermal pad is attached to a heat spreader (copper areas) by using a low-thermal-impedance attachment method (solder paste or thermal-conductive epoxy). In both of these cases, it is advisable to use as much copper and as many traces as possible to dissipate the heat.