SLIS150M March   2014  – June 2024 DRV5013

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Magnetic Characteristics
    8. 5.8 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Field Direction Definition
      2. 6.3.2 Device Output
      3. 6.3.3 Power-On Time
      4. 6.3.4 Output Stage
      5. 6.3.5 Protection Circuits
        1. 6.3.5.1 Overcurrent Protection (OCP)
        2. 6.3.5.2 Load Dump Protection
        3. 6.3.5.3 Reverse Supply Protection
    4. 6.4 Device Functional Modes
  8. Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Standard Circuit
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 Configuration Example
        3. 7.2.1.3 Application Curves
      2. 7.2.2 Alternative Two-Wire Application
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Device Nomenclature
      2. 8.1.2 Device Markings
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Power-On Time

After applying VCC to the DRV5013 device, ton must elapse before the OUT pin is valid. During the power-up sequence, the output is Hi-Z. A pulse as shown in Figure 6-4 and Figure 6-5 occurs at the end of ton. This pulse can allow the host processor to determine when the DRV5013 output is valid after start-up. The power-up sequence, including the pulse, is the same for all device output versions (AD, AG, BC, FA, ND). Case 1, 2, 3 and 4 below show examples of valid outputs for the non-inverted output versions (AD, AG, BC, FA). In Case 1 (Figure 6-4) and Case 2 (Figure 6-5), the output is defined assuming a constant magnetic flux density B > BOP and B < BRP.

DRV5013 Case 1: Power On When B >
            BOP Figure 6-4 Case 1: Power On When B > BOP
DRV5013 Case 2: Power On When B <
            BRP Figure 6-5 Case 2: Power On When B < BRP

If the device is powered on with the magnetic flux density BRP < B < BOP, then the device output is indeterminate and can either be Hi-Z or pulled low. During the power-up sequence, the output is held Hi-Z until ton has elapsed. At the end of ton, a pulse is given on the OUT pin to indicate that ton has elapsed. After ton, if the magnetic flux density changes such that BOP < B, the output is released. Case 3 (Figure 6-6) and Case 4 (Figure 6-7) show examples of this behavior.

DRV5013 Case 3: Power On When BRP
          < B < BOP, Followed by B > BOP Figure 6-6 Case 3: Power On When BRP < B < BOP, Followed by B > BOP
DRV5013 Case 4: Power On When BRP
          < B < BOP, Followed by B < BRP Figure 6-7 Case 4: Power On When BRP < B < BOP, Followed by B < BRP