SLIS150M March   2014  – June 2024 DRV5013

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Magnetic Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Field Direction Definition
      2. 6.3.2 Device Output
      3. 6.3.3 Power-On Time
      4. 6.3.4 Output Stage
      5. 6.3.5 Protection Circuits
        1. 6.3.5.1 Overcurrent Protection (OCP)
        2. 6.3.5.2 Load Dump Protection
        3. 6.3.5.3 Reverse Supply Protection
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Standard Circuit
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 Configuration Example
        3. 7.2.1.3 Application Curves
      2. 7.2.2 Alternative Two-Wire Application
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Device Nomenclature
      2. 8.1.2 Device Markings
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

7.2.2.2 Detailed Design Procedure

When the open-drain output of the device is high-impedance, current through the path equals the ICC of the device (approximately 3 mA).

When the output pulls low, a parallel current path is added, equal to VCC / (R1 + rDS(on)). Using 12 V and 1 kΩ, the parallel current is approximately 12 mA, making the total current approximately 15 mA.

The local bypass capacitor C1 should be at least 0.1 µF, and a larger value if there is high inductance in the power line interconnect.