SLIS178B October   2017  – January 2018 TPS92830-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Simplified Schematic
  4. 4 Revision History
  5. 5 Description (Continued)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Device Bias
        1. 8.3.1.1 Power-On-Reset (POR)
        2. 8.3.1.2 Current Reference (IREF)
        3. 8.3.1.3 Low-Current Fault Mode
      2. 8.3.2 Charge Pump
        1. 8.3.2.1 Charge Pump Architecture
      3. 8.3.3 Constant-Current Driving
        1. 8.3.3.1 High-Side Current Sense
        2. 8.3.3.2 High-Side Current Driving
        3. 8.3.3.3 Gate Overdrive Voltage Protection
        4. 8.3.3.4 High-Precision Current Regulation
        5. 8.3.3.5 Parallel MOSFET Driving
      4. 8.3.4 PWM Dimming
        1. 8.3.4.1 Supply Dimming
        2. 8.3.4.2 PWM Dimming by Input
        3. 8.3.4.3 Internal Precision PWM Generator
        4. 8.3.4.4 Full Duty-Cycle Switch
      5. 8.3.5 Analog Dimming
        1. 8.3.5.1 Analog Dimming Topology
        2. 8.3.5.2 Internal High-Precision Pullup Current Source
      6. 8.3.6 Output Current Derating
        1. 8.3.6.1 Output-Current Derating Topology
      7. 8.3.7 Diagnostics and Fault
        1. 8.3.7.1 LED Short-to-GND Detection
        2. 8.3.7.2 LED Short-to-GND Auto Retry
        3. 8.3.7.3 LED Open-Circuit Detection
        4. 8.3.7.4 LED Open-Circuit Auto Retry
        5. 8.3.7.5 Dropout-Mode Diagnostics
        6. 8.3.7.6 Overtemperature Protection
        7. 8.3.7.7 FAULT Bus Output With One-Fails–All-Fail
        8. 8.3.7.8 Fault Table
    4. 8.4 Device Functional Modes
      1. 8.4.1 Undervoltage Lockout, V(IN) < V(UVLO)
      2. 8.4.2 Normal Operation (V(IN) ≥ 4.5 V, V(IN) > V(LED) + 0.5 V)
      3. 8.4.3 Low-Voltage Dropout
      4. 8.4.4 Fault Mode (Fault Is Detected)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Typical Application for Automotive Exterior Lighting With One-Fails–All-Fail
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 High-Precision Dual-Brightness PWM Generation
        1. 9.2.2.1 Dual-Brightness Application
        2. 9.2.2.2 Design Requirements
        3. 9.2.2.3 Detailed Design Procedure
        4. 9.2.2.4 Application Curve
      3. 9.2.3 Driving High-Current LEDs With Parallel MOSFETs
        1. 9.2.3.1 Application Curves
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

7.5 Electrical Characteristics

VIN = 5 V to 40 V, VICTRL = 3 V, VDERATE = 0 V, TJ= –40°C to 150°C,(1) (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
BIAS
V(POR_rising) Supply voltage POR, rising threshold 4.5 V
I(Quiescent) Device standby current PWMx = HIGH, FD = HIGH 3.5 mA
I(FAULT) Device current in fault mode PWMx = HIGH, FAULT = LOW 0.5 0.75 mA
I(IREF) Reference current R(IREF) = 8 kΩ 99 µA
C(IREF) IREF loading capacitance R(IREF) = 8 kΩ 0 4.3 nF
CHARGE PUMP
V(cp_drv) Charge-pump operating voltage 6.1 8.5 10 V
f(cp_sw) Charge-pump switching frequency 2.65 MHz
C(cp_flying) Charge-pump flying capacitor 10 nF
C(cp_storage) Charge-pump storage capacitor 150 nF
HIGH-PRECISION LOGIC INPUTS (DIAGEN, PWMx, FD)
VIL(DIAGEN) Input logic-low voltage, DIAGEN 1.105 1.145 1.185 V
VIH(DIAGEN) Input logic-high voltage, DIAGEN 1.193 1.224 1.255 V
VIL(PWMx) Input logic-low voltage, PWMx 1.094 1.128 1.161 V
VIH(PWMx) Input logic-high voltage, PWMx 1.176 1.212 1.248 V
VIL(FD) Input logic-low voltage, FD 1.105 1.133 1.161 V
VIH(FD) Input logic-high voltage, FD 1.186 1.216 1.246 V
CONSTANT-CURRENT EXTERNAL N-CHANNEL MOSFET DRIVER
V(CS_REG_FULL) Current-sense-resistor regulation voltage V(ICTRL) = 3 V, V(DERATE) = 0 V 295 mV
∆V(CS)(2)(3) Current-sense-resistor regulation-voltage accuracy V(ICTRL) = 3 V, V(DERATE) = 0 V, channel accuracy –1.5% 1.5%
V(ICTRL) = 3 V, V(DERATE) = 0 V, device accuracy –2.5% 2.5%
I(DRV_source) Gate-driver current-source capability at Gx 190 230 270 µA
I(DRV_sink) Gate-driver current-sink capability at Gx 190 230 270 µA
V(GS_clamp_neg) Gate-source negative clamp voltage –0.9 –0.7 –0.5 V
V(GS_clamp_pos) Gate-source positive clamp voltage 9.8 10.4 11.3 V
I(ISNx_leakage) Leakage current sink on ISNx pins 1.3 2.3 µA
INTERNAL PWM DIMMING
V(PWMCHG_th_rising) Internal PWM generator, rising threshold 1.45 1.48 1.51 V
V(PWMCHG_th_falling) Internal PWM generator, falling threshold 0.78 0.8 0.82 V
V(PWMCHG_th_hys) Internal PWM generator hysteresis 0.68 V
I(PWMCHG) PWM generator pullup current V(PWMCHG) = 0 V, FD = LOW 194 200 206 µA
VOL(PWMOUT) Open-drain PWMOUT pulldown voltage V(PWMCHG) = 3 V, I(PWMOUT) pullup current = 4 mA 0.4 V
rDS(on)(PWMOUT) Open-drain PWMOUT pulldown MOSFET rDS(on) 40 55 90 Ω
ANALOG DIMMING
V(ICTRL_FULL) Full-range ICTRL voltage 1.65 V
V(ICTRL_LIN_TOP) Upper boundary for linear ICTRL dimming 1.425 V
V(ICTRL_LIN_BOT) Lower boundary for linear ICTRL dimming 75 mV
∆V(CS_ ICTRL_H) Analog dimming accuracy V(ICTRL) = 1.35 V, V(DERATE) = 0 V, accuracy: 1 – (V(CS_REG_x) / 0.27), x = 1, 2, 3 –2.5% 2%
∆V(CS_ ICTRL_M) Analog dimming accuracy V(ICTRL) = 0.75 V, V(DERATE) = 0 V, accuracy: 1 – (V(CS_REG_x) / 0.15), x = 1, 2, 3 –4% 4%
∆V(CS_ ICTRL_L) Analog dimming accuracy V(ICTRL) = 0.15 V, V(DERATE) = 0 V, accuracy: 1 –V(CS_REG_x) / 0.03, x = 1, 2, 3 –18% 18%
I(ICTRL_pullup) ICTRL internal pullup current 0.95 0.985 1.02 mA
CURRENT DERATING
V(DERATE_FULL) Full-range DERATE voltage 1.83 V
V(DERATE_HALF) Half-range DERATE voltage 2.38 V
K(DERATE) Derate dimming ratio V(DERATE) = 1.966 V 81% 87% 95%
V(DERATE) = 2.316 V 51% 58% 65%
DIAGNOSTICS
V(OPEN_th_rising) LED open rising threshold, device triggers open-circuit diagnostics V(SG_th_rising), and V(SG_th_falling) in the Electrical Characteristics table V(ISNx) – V(SENSEx), x = 1, 2, 3 100 145 190 mV
V(OPEN_th_falling) LED open falling threshold, device releases from open-circuit diagnostics V(ISNx) – V(SENSEx), x = 1, 2, 3 240 280 320 mV
V(OPEN_th_hyst) 135 mV
I(Retry_open) LED-open retry current 8 10 12 mA
V(SG_th_rising) Channel output VSENSEx short-to-ground rising threshold, device triggers short-to-ground diagnostics 0.885 0.92 0.95 V
V(SG_th_falling) Channel output VSENSEx short-to-ground falling threshold, device releases from short-to-ground diagnostics 1.17 1.215 1.26 V
V(SG_th_hyst) Channel output VSENSEx short-to-ground hysteresis 295 mV
I(Retry_short) Channel output VSENSEx short-to-ground retry current 0.75 1 1.25 mA
FAULT
VIL(FAULT) Logic-input low threshold 0.7 V
VIH(FAULT) Logic-input high threshold 2 V
VOL(FAULT) Logic-output low threshold With 500-µA external pullup 0.4 V
VOH(FAULT) Logic-output high threshold With 1-µA external pulldown 2.7 3.4 V
I(FAULT_pulldown) FAULT internal pulldown current 650 750 800 µA
I(FAULT_pullup) FAULT internal pullup current 6.5 7.6 9.5 µA
THERMAL PROTECTION
T(TSD) Thermal shutdown threshold 176 ºC
T(TSD_HYS) Thermal shutdown hysteresis 15 ºC
(1) External N-channel MOSFET Ciss = 200 pF, Coss = 70 pF, at VDS = 25 Vdc, VGS = 0 Vdc, f = 1 MHz, Vth= 4 V, compensation capacitor Cgs = 4 nF
(2) TPS92830-Q1 Equation_08_SLIS178.gif
(3) TPS92830-Q1 Equation_09_SLIS178.gif