SLLA475 December   2020 TCAN1144-Q1 , TCAN1146-Q1

 

  1. 1TCAN1144-Q1 and TCAN1146-Q1 Functional Safety Manual
  2. 2Trademarks
  3. 3Introduction
  4. 4TCAN114x-Q1 Hardware Component Functional Safety Capability
  5. 5Development Process for Management of Systematic Faults
    1. 5.1 TI New-Product Development Process
  6. 6TCAN1144-Q1 and TCAN1146-Q1 Component Overview
    1. 6.1 Targeted Applications
    2. 6.2 Hardware Component Functional Safety Concept
    3. 6.3 Functional Safety Constraints and Assumptions
  7. 7Description of Hardware Component Parts
    1. 7.1 CAN Transceiver
    2. 7.2 Digital Core
    3. 7.3 EEPROM
    4. 7.4 Power Control IP
      1. 7.4.1 Voltage Monitors
    5. 7.5 Thermal Shut Down
    6. 7.6 Digital Input/Outputs
  8. 8TCAN1144-Q1 and TCAN1146-Q1 Management of Random Faults
    1. 8.1 Fault Reporting
    2. 8.2 Functional Safety Mechanism Categories
    3. 8.3 Description of Functional Safety Mechanisms
      1. 8.3.1 CAN Communication
        1. 8.3.1.1 SM-1: CAN bus fault diagnostic
        2. 8.3.1.2 SM-2: Thermal shutdown; TSD
        3. 8.3.1.3 SM-3: CAN bus short circuit limiter, IOS
        4. 8.3.1.4 SM-4: CAN TXD pin dominant state timeout; tTXD_DTO
        5. 8.3.1.5 SM-17: CAN protocol
      2. 8.3.2 Supply Voltage Rail Monitoring
        1. 8.3.2.1 SM-5: VCC undervoltage; UVCC
        2. 8.3.2.2 SM-6: VSUP supply undervoltage; UVSUP
        3. 8.3.2.3 SM-7: VIO supply undervoltage; UVIO
      3. 8.3.3 SPI/Processor Communication
        1. 8.3.3.1 SM-8: Timout, Window or Q&A watchdog error - Normal mode
        2. 8.3.3.2 SM-9: SPI communication error; SPIERR
        3. 8.3.3.3 SM-10: Scratchpad write/read
        4. 8.3.3.4 SM-11: Sleep Wake Error Timer; tINACTIVE
      4. 8.3.4 Device Internal EEPROM
        1. 8.3.4.1 SM-12: Internal memory CRC; CRC_EEPROM
      5. 8.3.5 Floating Pins
        1. 8.3.5.1 SM-13: SCLK internal pull-up to VIO
        2. 8.3.5.2 SM-14: SDI internal pull-up to VIO
        3. 8.3.5.3 SM-15: nCS internal pull-up to VIO
        4. 8.3.5.4 SM-16: TXD internal pull-up to VIO
          1.        B Revision History

8.3.1.4 SM-4: CAN TXD pin dominant state timeout; tTXD_DTO

The TCAN1144-Q1 and TCAN1146-Q1 supports dominant state time out (DTO). This is an internal function based upon the TXD path. The TXD DTO circuit prevents the local node from blocking network communication in event of a hardware or software failure where TXD is held dominant (LOW) longer than the time out period tTXD_DTO. The TXD DTO circuit is triggered by a falling edge on TXD. If no rising edge is seen before the time out constant of the circuit, tTXD_DTO, the CAN driver is disabled. This frees the bus for communication between other nodes on the network. The CAN driver is re-activated when a recessive signal (HIGH) is seen on TXD terminal; thus, clearing the dominant time out. The receiver remains active and the RXD terminal reflects the activity on the CAN bus and the bus terminals is biased to recessive level during a TXD DTO fault. This feature can be disabled by using register 8'h10[6] = 1b, DTO_DIS.

Note: The minimum dominant TXD time allowed by the TXD DTO circuit limits the minimum possible transmitted data rate of the device. The CAN protocol allows a maximum of eleven successive dominant bits (on TXD) for the worst case, where five successive dominant bits are followed immediately by an error frame.