SLLA535 December   2022 TLIN1431-Q1

 

  1. 1Introduction
    1.     Trademarks
  2. 2TLIN1431x-Q1 Hardware Component Functional Safety Capability
  3. 3Development Process for Management of Systematic Faults
    1. 3.1 TI New-Product Development Process
    2. 3.2 TI Functional Safety Development Process
  4. 4TLIN1431x-Q1 Component Overview
    1. 4.1 Targeted Applications
    2. 4.2 Hardware Component Functional Safety Concept
    3. 4.3 Functional Safety Constraints and Assumptions
  5. 5Description of Hardware Component Parts
    1. 5.1 LIN Transceiver
    2. 5.2 Digital Core
    3. 5.3 Power Control IP
    4. 5.4 Digital Input/Output Pins and High-side Switch
  6. 6TLIN1431x-Q1 Management of Random Faults
    1. 6.1 Fault Reporting
    2. 6.2 Functional Safety Mechanism Categories
    3. 6.3 Description of Functional Safety Mechanisms
      1. 6.3.1 LIN Bus and Communication
        1. 6.3.1.1 SM-1: LIN TXD Pin Dominant State Timeout
        2. 6.3.1.2 SM-2: LIN Bus Stuck Dominant System Fault: False Wake Up Lockout
        3. 6.3.1.3 SM-3: LIN Bus Short Circuit Limiter
        4. 6.3.1.4 SM-20: LIN Internal pull-up to VSUP
        5. 6.3.1.5 SM-22: LIN Protocol
      2. 6.3.2 Voltage Rail Monitoring
        1. 6.3.2.1 SM-4: VCC and Transceiver Thermal Shutdown
        2. 6.3.2.2 SM-5: VCC Under-voltage
        3. 6.3.2.3 SM-6: VCC Over-voltage
        4. 6.3.2.4 SM-7: VCC Short to Ground
        5. 6.3.2.5 SM-8: VSUP Under-voltage
      3. 6.3.3 Processor Communication
        1. 6.3.3.1 SM-9 and SM-10: Watchdog
          1. 6.3.3.1.1 SM-9: Standby Mode Long Window Timeout Watchdog
          2. 6.3.3.1.2 SM-10: Normal Mode Watchdog
        2. 6.3.3.2 SM-11: SPI CRC
        3. 6.3.3.3 SM-12: SPI Communication Error; SPIERR
        4. 6.3.3.4 SM-13: Scratchpad Write/Read Register
        5. 6.3.3.5 SM-14: Sleep Wake Error Timer; tINACT_FS
      4. 6.3.4 Digital Input/Output Pins and High-side Switch
        1. 6.3.4.1 SM-15: CLK internal pull-up to VINT
        2. 6.3.4.2 SM-16: SDI internal pull-up to VINT
        3. 6.3.4.3 SM-17: nCS Internal pull-up to VINT
        4. 6.3.4.4 SM-18: DIV_ON Internal pull-down to GND
        5. 6.3.4.5 SM-19: TXD Internal pull-up to VINT
        6. 6.3.4.6 SM-21: nRST Internal pull-up to VINT
        7. 6.3.4.7 SM-23: HSS Over Current Detect
        8. 6.3.4.8 SM-24: HSS Open Load Detect
          1.        A Summary of Recommended Functional Safety Mechanism Usage
            1.         B Distributed Developments
              1.          B.1 How the Functional Safety Lifecycle Applies to TI Functional Safety Products
              2.          B.2 Activities Performed by Texas Instruments
              3.          B.3 Information Provided
                1.           C Revision History

6.1 Fault Reporting

The TLIN1431x-Q1 when configured for SPI control utilizes interrupt registers for fault reporting. The global interrupt register, 8'h50[7:0] provides information on where to find other interrupts that provide more detailed information on a fault, registers 8'h51 - 8'h53 and 8'h5A.

Table 6-1 INT_GLOBAL Register Field Descriptions (Address = 50h)
BitFieldTypeResetDescription
7GLOBALERRRH1bLogical OR of all interrupts
6INT_1RH0bLogical OR of INT_1 register
5INT_2RH1bLogical OR of INT_2 register
4INT_3RH0bLogical OR of INT_3 register
3RSVDR0bReserved
2INT_4RH0bLogical OR of INT_4 register
1-0RSVDR0bReserved
Table 6-2 INT_1 Register Field Descriptions (Address = 51h)
BitFieldTypeResetDescription
7WDR/W1C0bWatchdog event interrupt.
NOTE: This interrupt bit is set for every watchdog error event and does not rely upon the Watchdog error counter
6RSVDR0bReserved
5LWUR/W1C0bLocal wake up
4WKERRR/W1C0bWake error bit is set when the SWE timer has expired and the state machine has returned to Sleep mode
3-0RSVDR0bReserved
Table 6-3 INT_2 Register Field Descriptions (Address = 52h)
BitFieldTypeResetDescription
7SMSR/W1C0bSleep mode status flag. Only sets when sleep mode is entered by a fault
6PWRONR/W1C1bPower on
5OVCCR/W1C0bVCC overvoltage
4UVSUPR/W1C0bVSUP undervoltage
3RSVDR0bReserved
2UVCCR/W1C0bVCC undervoltage
1TSD_VCC_LINR/W1C0bThermal Shutdown due to VCC or LIN
0TSD_HSS_LIMPR/W1C0bThermal Shutdown due to HSS or LIMP
Table 6-4 INT_3 Register Field Descriptions (Address = 53h)
BitFieldTypeResetDescription0b
7SPIERRR/W1C0bSets when SPI status bit sets
6RSVDR0bReserved
5FSMR/W1C0bEntered fail-safe mode. Can be cleared while in failsafe mode.
4CRCERRR/W1C/U0bSPI CRC error detected
3VCCSCR/W1C/U0bVCC short detected
2RSRT_CNTR/W1C/U0bRestart counter exceeded programmed count
1-0RSVDR0bReserved
Table 6-5 INT_4 Register Field Descriptions (Address = 5Ah)
BitFieldTypeResetDescription
7LIN_WUPR/W1C0bLIN bus wake
6LIN_DTOR/W1C0bLIN dominant state timeout
5-4RSVDR00bReserved
3HSSOCR/W1C0bHigh side switch over current
2HSSOLR/W1C0bHigh side switch open load
1-0RSVDR00bReserved